Fix for target register mismatched len

This commit is contained in:
lcbcfoo 2018-10-07 16:31:54 -03:00
parent c583fce996
commit dc4d738bed

View file

@ -3662,7 +3662,7 @@ begin
-- Get rd and set write enable and other LEON3 signals
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd, de_rexen);
v.a.ctrl.rd := de_rd(4 downto 0);
v.a.ctrl.rd(4 downto 0) := de_rd(4 downto 0);
-- No RISC-V FP unit
-- fpbranch(de_inst, fpo.cc, de_fbranch);