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61 lines
1.1 KiB
Tcl
61 lines
1.1 KiB
Tcl
# Synplicity, Inc. constraint file
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# /home/jiri/ibm/vhdl/grlib/boards/gr-cpci-xc2v/default.sdc
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# Written on Mon Feb 14 11:45:37 2005
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# by Synplify Pro, Synplify Pro 8.0 Scope Editor
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#
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# Collections
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#
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#
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# Clocks
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#
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define_clock -disable -name {clk} -freq 50.000 -clockgroup default_clkgroup
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define_clock -disable -name {pci_clk} -freq 40.000 -clockgroup pci_clkgroup
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define_clock -disable -name {usb_clkout} -freq 60.000 -clockgroup usb_clkgroup
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#
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# Clock to Clock
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#
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#
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# Inputs/Outputs
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#
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define_output_delay -disable -default 14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_input_delay -disable -default 14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_output_delay -disable -default 14.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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define_input_delay -disable -default 18.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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define_input_delay -disable {pci_rst} 0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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#
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# Registers
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#
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#
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# Multicycle Path
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#
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#
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# False Path
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#
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#
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# Path Delay
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#
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#
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# Attributes
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#
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define_global_attribute syn_useioff {1}
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#
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# I/O standards
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#
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#
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# Compile Points
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#
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#
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# Other Constraints
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#
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