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61 lines
1.3 KiB
Tcl
61 lines
1.3 KiB
Tcl
# Synplicity, Inc. constraint file
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# /home/magnus/grlib-gpl-1.0.18-b2950/boards/xilinx-spa3-dsp1800a/default.sdc
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# Written on Mon Jul 21 10:31:29 2008
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# by Synplify Pro, Synplify Pro 8.9 Scope Editor
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#
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# Collections
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#
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#
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# Clocks
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#
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define_clock {clk27} -name {clk27} -freq 30 -clockgroup default_clkgroup -route 0
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define_clock {clk200_p} -name {clk200_p} -freq 200 -clockgroup ddr2_clkgroup -route 0
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define_clock {clkm} -name {clkm} -freq 80 -clockgroup main_clkgroup -route 0
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define_clock {clkml} -name {clkml} -freq 135 -clockgroup ddr_clkgroup -route 0
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define_clock {etx_clk} -name {etx_clk} -freq 25 -clockgroup phy_rx_clkgroup -route 0
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define_clock {erx_clk} -name {erx_clk} -freq 25 -clockgroup phy_tx_clkgroup -route 0
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#
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# Clock to Clock
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#
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#
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# Inputs/Outputs
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#
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define_output_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_input_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r}
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#
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# Registers
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#
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#
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# Multicycle Path
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#
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#
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# False Path
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#
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#
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# Path Delay
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#
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#
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# Attributes
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define_global_attribute syn_useioff {1}
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#
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# I/O standards
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# Compile Points
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#
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#
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# Other Constraints
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#
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