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85 lines
2.5 KiB
Text
85 lines
2.5 KiB
Text
LEON3 ASIC template design
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---------------------------
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Overview
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--------
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This LEON3 design demonstrates how to make use of the created GRLIB
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scripts in Design Complier and to verify the generated netlist via
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gate-level simulation and formal equivalence check.
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Note: The Design Compiler flow and parts of this design are still
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experimental. Currently the leon3-asic design configuration only has
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support for a few of the techmap options available. Default is the
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Synopsys 32/28nm Generic Library for Teaching i.e. SAED32. The library
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can be downloaded from www.synopsys.com
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To compile and simulate the design you will need to modify the file:
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SAED32_EDK/lib/pll/verilog/PLL.v
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and comment out the VDD and VSS ports.
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Simulation and synthesis
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------------------------
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The user needs to specify the path to the installation of the ASIC
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library used in the technology setup file. For SAED32 the user needs
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to set the variable SAED32_HOME. This can be set directly in the
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design's Makefile. SAED32_HOME should point at the directory
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containing SAED32_EDK.
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To simulate using Modelsim/Aldec and run systest.c on the LEON3 ASIC
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design:
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make comp_saed32_sim (If SAED32 is used)
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make sim
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make soft
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make vsim-launch
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Synthesis has been tested using Design Compiler 2013.3-SP1 installed or newer, and
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the SYNOPSYS variable properly set in the shell. To synthesize the design, do
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make dc
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Simulation options
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------------------
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All options are set either by editing the testbench or specify/modify the generic
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default value when launching the simulator. For Modelsim use the option "-g" i.e.
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to enable processor disassembly to console launch modelsim with the option: "-gdisas=1"
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disas - Enable processor disassembly to console
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Memory tests
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------------
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All on-chip RAM blocks are tested by writing and checking
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the following values: 0x55555555, 0xAAAAAAAA, address pattern.
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This will insure that all bits are tested to both 0 and 1,
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and that the address decoder is tested. Additional patterns
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can be added but will result in increased number of test
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vectors.
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Design specifics
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----------------
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* Simulation has been tested using Modelsim 10.1 or newer
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* Synthesis should be done using Design Compiler 2013.3-SP1 or newer
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* Formal verification should be done using Formality 2013.3-SP4 or newer
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* ASIC Technology is expected to be integrated into GRLIB
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* Dual-use pins in test mode:
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scanin -> dsurx
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scanout -> dsutx
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scanen -> dsubre
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testrst -> dsuen
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inoutct -> rxd1
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testmode -> test
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scanclk -> clk
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