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270 lines
12 KiB
VHDL
270 lines
12 KiB
VHDL
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2013, Aeroflex Gaisler AB
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.jtag.all;
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use work.config.all;
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entity bschain is
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generic (tech: integer := CFG_FABTECH;
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enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
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hzsup: integer range 0 to 1 := 1);
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port (
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-- Chain control signals
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chain_tck : in std_ulogic;
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chain_tckn : in std_ulogic;
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chain_tdi : in std_ulogic;
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chain_tdo : out std_ulogic;
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bsshft : in std_ulogic;
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bscapt : in std_ulogic;
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bsupdi : in std_ulogic;
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bsupdo : in std_ulogic;
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bsdrive : in std_ulogic;
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bshighz : in std_ulogic;
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-- Pad-side signals
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Presetn : in std_ulogic;
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Pclksel : in std_logic_vector (1 downto 0);
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Pclk : in std_ulogic;
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Perrorn : out std_ulogic;
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Paddress : out std_logic_vector(27 downto 0);
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Pdatain : in std_logic_vector(31 downto 0);
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Pdataout : out std_logic_vector(31 downto 0);
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Pdataen : out std_logic_vector(31 downto 0);
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Pcbin : in std_logic_vector(7 downto 0);
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Pcbout : out std_logic_vector(7 downto 0);
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Pcben : out std_logic_vector(7 downto 0);
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Psdclk : out std_ulogic;
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Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
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Psdwen : out std_ulogic; -- sdram write enable
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Psdrasn : out std_ulogic; -- sdram ras
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Psdcasn : out std_ulogic; -- sdram cas
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Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
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Pdsutx : out std_ulogic; -- DSU tx data
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Pdsurx : in std_ulogic; -- DSU rx data
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Pdsuen : in std_ulogic;
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Pdsubre : in std_ulogic;
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Pdsuact : out std_ulogic;
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Ptxd1 : out std_ulogic; -- UART1 tx data
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Prxd1 : in std_ulogic; -- UART1 rx data
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Ptxd2 : out std_ulogic; -- UART2 tx data
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Prxd2 : in std_ulogic; -- UART2 rx data
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Pramsn : out std_logic_vector (4 downto 0);
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Pramoen : out std_logic_vector (4 downto 0);
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Prwen : out std_logic_vector (3 downto 0);
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Poen : out std_ulogic;
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Pwriten : out std_ulogic;
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Pread : out std_ulogic;
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Piosn : out std_ulogic;
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Promsn : out std_logic_vector (1 downto 0);
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Pbrdyn : in std_ulogic;
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Pbexcn : in std_ulogic;
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Pwdogn : out std_ulogic;
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Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Pprom32 : in std_ulogic;
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Ppromedac : in std_ulogic;
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Pspw_clksel : in std_logic_vector (1 downto 0);
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Pspw_clk : in std_ulogic;
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Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
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Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
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Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
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Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
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Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
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Plclk2x : in std_ulogic;
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Plclk4x : in std_ulogic;
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Plclkdis : out std_ulogic;
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Plclklock : in std_ulogic;
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Plock : out std_ulogic;
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Proen : in std_ulogic;
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Proout : out std_ulogic;
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-- Core-side signals
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Cresetn : out std_ulogic;
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Cclksel : out std_logic_vector (1 downto 0);
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Cclk : out std_ulogic;
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Cerrorn : in std_ulogic;
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Caddress : in std_logic_vector(27 downto 0);
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Cdatain : out std_logic_vector(31 downto 0);
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Cdataout : in std_logic_vector(31 downto 0);
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Cdataen : in std_logic_vector(31 downto 0);
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Ccbin : out std_logic_vector(7 downto 0);
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Ccbout : in std_logic_vector(7 downto 0);
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Ccben : in std_logic_vector(7 downto 0);
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Csdclk : in std_ulogic;
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Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
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Csdwen : in std_ulogic; -- sdram write enable
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Csdrasn : in std_ulogic; -- sdram ras
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Csdcasn : in std_ulogic; -- sdram cas
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Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
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Cdsutx : in std_ulogic; -- DSU tx data
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Cdsurx : out std_ulogic; -- DSU rx data
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Cdsuen : out std_ulogic;
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Cdsubre : out std_ulogic;
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Cdsuact : in std_ulogic;
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Ctxd1 : in std_ulogic; -- UART1 tx data
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Crxd1 : out std_ulogic; -- UART1 rx data
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Ctxd2 : in std_ulogic; -- UART2 tx data
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Crxd2 : out std_ulogic; -- UART2 rx data
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Cramsn : in std_logic_vector (4 downto 0);
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Cramoen : in std_logic_vector (4 downto 0);
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Crwen : in std_logic_vector (3 downto 0);
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Coen : in std_ulogic;
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Cwriten : in std_ulogic;
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Cread : in std_ulogic;
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Ciosn : in std_ulogic;
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Cromsn : in std_logic_vector (1 downto 0);
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Cbrdyn : out std_ulogic;
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Cbexcn : out std_ulogic;
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Cwdogn : in std_ulogic;
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Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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Cprom32 : out std_ulogic;
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Cpromedac : out std_ulogic;
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Cspw_clksel : out std_logic_vector (1 downto 0);
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Cspw_clk : out std_ulogic;
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Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
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Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
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Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
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Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
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Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
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Clclk2x : out std_ulogic;
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Clclk4x : out std_ulogic;
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Clclkdis : in std_ulogic;
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Clclklock : out std_ulogic;
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Clock : in std_ulogic;
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Croen : out std_ulogic;
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Croout : in std_ulogic
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);
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end;
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architecture rtl of bschain is
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signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
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signal sr1i, sr1o: std_logic_vector(4 downto 0);
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signal sr3i, sr3o: std_logic_vector(41 downto 0);
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signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Scan chain registers (note: adjust order to match pad ring)
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sr1a: bscanregs
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generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
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port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
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Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
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Cclk <= sr1o(1); Perrorn <= sr1o(0);
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sr1b: bscanregs
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generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
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port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr2a: bscanregsbd
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generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
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port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
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chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr2b: bscanregsbd
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generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
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port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
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chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr3a: bscanregs
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generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
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port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr3b: bscanregs
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generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
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port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
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Csddqm & Cdsutx & Pdsurx;
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sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
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sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
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sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
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Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
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Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
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Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
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Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
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Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
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Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
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Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
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Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
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Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
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sr4: bscanregsbd
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generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
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port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
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chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr5: bscanregs
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generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
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port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
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Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
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Clclkdis & Plclklock & Clock & Proen & Croout;
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Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
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Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
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Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
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Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
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Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
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Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
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Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
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Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
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Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
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Clclk2x <= sr5o(6);
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Clclk4x <= sr5o(5);
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Plclkdis <= sr5o(4);
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Clclklock <= sr5o(3);
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Plock <= sr5o(2);
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Croen <= sr5o(1);
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Proout <= sr5o(0);
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end;
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