mirror of
https://github.com/lcbcFoo/ReonV.git
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301 lines
11 KiB
VHDL
301 lines
11 KiB
VHDL
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2013 Aeroflex Gaisler AB
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.misc.all;
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use gaisler.jtag.all;
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use work.config.all;
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entity core is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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scantest : integer := CFG_SCAN;
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bscanen : integer := CFG_BOUNDSCAN_EN;
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oepol : integer := 0
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);
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port (
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resetn : in std_ulogic;
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clksel : in std_logic_vector (1 downto 0);
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clk : in std_ulogic;
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lock : out std_ulogic;
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errorn : out std_ulogic;
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address : out std_logic_vector(27 downto 0);
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datain : in std_logic_vector(31 downto 0);
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dataout : out std_logic_vector(31 downto 0);
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dataen : out std_logic_vector(31 downto 0);
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cbin : in std_logic_vector(7 downto 0);
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cbout : out std_logic_vector(7 downto 0);
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cben : out std_logic_vector(7 downto 0);
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sdclk : out std_ulogic;
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sdcsn : out std_logic_vector (1 downto 0);
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sdwen : out std_ulogic;
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sdrasn : out std_ulogic;
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sdcasn : out std_ulogic;
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sddqm : out std_logic_vector (3 downto 0);
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dsutx : out std_ulogic;
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dsurx : in std_ulogic;
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dsuen : in std_ulogic;
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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txd1 : out std_ulogic;
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rxd1 : in std_ulogic;
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txd2 : out std_ulogic;
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rxd2 : in std_ulogic;
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ramsn : out std_logic_vector (4 downto 0);
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ramoen : out std_logic_vector (4 downto 0);
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rwen : out std_logic_vector (3 downto 0);
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oen : out std_ulogic;
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writen : out std_ulogic;
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read : out std_ulogic;
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iosn : out std_ulogic;
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romsn : out std_logic_vector (1 downto 0);
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brdyn : in std_ulogic;
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bexcn : in std_ulogic;
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wdogn : out std_ulogic;
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gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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i2c_sclout : out std_ulogic;
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i2c_sclen : out std_ulogic;
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i2c_sclin : in std_ulogic;
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i2c_sdaout : out std_ulogic;
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i2c_sdaen : out std_ulogic;
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i2c_sdain : in std_ulogic;
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spi_miso : in std_ulogic;
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spi_mosi : out std_ulogic;
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spi_sck : out std_ulogic;
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spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
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prom32 : in std_ulogic;
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spw_clksel : in std_logic_vector (1 downto 0);
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spw_clk : in std_ulogic;
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spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
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gtx_clk : in std_ulogic;
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erx_clk : in std_ulogic;
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erxd : in std_logic_vector(7 downto 0);
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erx_dv : in std_ulogic;
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etx_clk : in std_ulogic;
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etxd : out std_logic_vector(7 downto 0);
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etx_en : out std_ulogic;
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etx_er : out std_ulogic;
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erx_er : in std_ulogic;
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erx_col : in std_ulogic;
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erx_crs : in std_ulogic;
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emdint : in std_ulogic;
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emdioin : in std_logic;
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emdioout : out std_logic;
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emdioen : out std_logic;
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emdc : out std_ulogic;
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testen : in std_ulogic;
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trst : in std_ulogic;
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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tdoen : out std_ulogic;
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chain_tck : out std_ulogic;
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chain_tckn : out std_ulogic;
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chain_tdi : out std_ulogic;
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chain_tdo : in std_ulogic;
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bsshft : out std_ulogic;
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bscapt : out std_ulogic;
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bsupdi : out std_ulogic;
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bsupdo : out std_ulogic;
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bsdrive : out std_ulogic;
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bshighz : out std_ulogic
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);
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end;
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architecture rtl of core is
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signal vcc : std_logic_vector(15 downto 0);
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signal gnd : std_ulogic;
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signal clk1x : std_ulogic;
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signal clk2x : std_ulogic;
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signal clk4x : std_ulogic;
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signal clk8x : std_ulogic;
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signal lclk : std_ulogic;
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-- signal lclkapb : std_ulogic;
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signal lspw_clk : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal lgtx_clk : std_ulogic;
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signal lerx_clk : std_ulogic;
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signal letx_clk : std_ulogic;
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signal llock : std_ulogic;
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signal scanen : std_ulogic;
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signal testrst : std_ulogic;
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signal testoen : std_ulogic;
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signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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begin
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-- Scan test mux logic not connected boundary scan chain
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scanen <= dsubre when (testen = '1' and scantest = 1) else '0';
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testrst <= dsuen when (testen = '1' and scantest = 1) else '1';
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testoen <= dsurx when (testen = '1' and scantest = 1) else '0';
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-- PLL for system clock
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clkgen0: clkgen
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generic map(
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tech => CFG_CLKTECH,
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clk_mul => CFG_CLKMUL,
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clk_div => CFG_CLKDIV,
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noclkfb => CFG_CLK_NOFB,
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freq => 50000)
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port map(
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clkin => clk,
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pciclkin => clk,
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clk => clk1x,
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clkn => open,
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clk2x => clk2x,
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sdclk => open,
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pciclk => open,
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cgi => cgi,
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cgo => cgo,
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clk4x => clk4x,
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clk1xu => open,
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clk2xu => open,
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clkb => open,
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clkc => open,
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clk8x => open);
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cgi.pllrst <= resetn;
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cgi.pllref <= lclk; -- Note: Used as fbclk if CFG_CLK_NOFB = 0
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cgi.clksel <= (others => '0');
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-- PLL is bypassed, and disabled, when either testen(0) = 1 or clksel =
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-- "00". Bit 0 of pllctrl input is used as the disable signal
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cgi.pllctrl(0) <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else '0';
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cgi.pllctrl(1) <= '0';
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-- Simulate lock signal when PLL not used
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llock <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else cgo.clklock;
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lock <= llock;
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-- Clock muxing inside boundary scan chain for CORE clock
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core_clock_mux : entity work.core_clock_mux
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generic map(
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tech => fabtech,
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scantest => scantest)
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port map(
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clksel => clksel,
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testen => testen,
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clkin => clk,
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clk1x => clk1x,
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clk2x => clk2x,
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clk4x => clk4x,
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clkout => lclk);
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-- Clock muxing inside boundary scan chain for APB CORE clock
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--apb_core_clock_mux : entity work.core_clock_mux
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-- generic map(
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-- tech => fabtech,
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-- scantest => scantest)
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-- port map(
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-- clksel => clksel,
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-- testen => testen,
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-- clkin => clk,
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-- clk1x => clk1x,
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-- clk2x => clk1x,
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-- clk4x => clk1x,
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-- clkout => lclkapb);
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-- Clock muxing inside boundary scan chain for SPW clock
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spw_core_clock_mux : entity work.core_clock_mux
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generic map(
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tech => fabtech,
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scantest => scantest)
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port map(
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clksel => spw_clksel,
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testen => testen,
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clkin => clk,
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clk1x => spw_clk,
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clk2x => spw_clk,
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clk4x => spw_clk,
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clkout => lspw_clk);
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-- Ethernet Clock Mux for scan test
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gtxclkmux : clkmux generic map (tech => fabtech) port map (gtx_clk,clk,testen,lgtx_clk);
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rxclkclkmux : clkmux generic map (tech => fabtech) port map (erx_clk,clk,testen,lerx_clk);
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txclkclkmux : clkmux generic map (tech => fabtech) port map (etx_clk,clk,testen,letx_clk);
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-- Clock outputs
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sdclk <= lclk;
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-- Control the GPIO direction during test
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-- Scantest mode. Lower half of the gpio are scan chain inputs in testmode
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-- and upper half of the gpio are outputs, i.e. maximum number of scan
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-- chains is the half number of GPIOs
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-- Note: testen and testoen should have priority over resetn because the registers
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-- in the reset generator are part of the scan chain, and the direction
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-- of gpio(23:12) would then depend on the value of a register in the
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-- scan chain.
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gpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2)) <= lgpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2))
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when (testoen = '0') else (others => '0') when oepol = 1 else (others => '1');
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gpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0) <= lgpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0)
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when (testoen = '0') else (others => '1') when oepol = 1 else (others => '0');
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leon3core0 : entity work.leon3core
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generic map ( fabtech, memtech, padtech, clktech, disas, dbguart,
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pclow, scantest*(1 - is_fpga(fabtech)))
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port map (
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resetn, clksel, lclk, lclk, --lclkapb,
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llock, errorn,
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address, datain, dataout, dataen, cbin, cbout, cben,
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sdcsn, sdwen, sdrasn, sdcasn, sddqm,
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dsutx, dsurx, dsuen, dsubre, dsuact,
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txd1, rxd1, txd2, rxd2,
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ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn,
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wdogn, gpioin, gpioout, lgpioen,
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i2c_sclout, i2c_sclen, i2c_sclin, i2c_sdaout, i2c_sdaen, i2c_sdain,
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spi_miso, spi_mosi, spi_sck, spi_slvsel,
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prom32,
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spw_clksel,lspw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
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lgtx_clk, lerx_clk, erxd, erx_dv, letx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdioin, emdioout, emdioen, emdc ,
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trst, tck, tms, tdi, tdo, tdoen,
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scanen, testen, testrst, testoen,
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chain_tck, chain_tckn, chain_tdi, chain_tdo,
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bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
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end;
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