mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-24 05:27:07 -04:00
504 lines
18 KiB
VHDL
504 lines
18 KiB
VHDL
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2013 Aeroflex Gaisler AB
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.config.all;
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library techmap;
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use techmap.gencomp.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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scantest : integer := CFG_SCAN
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);
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port (
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resetn : in std_ulogic;
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clksel : in std_logic_vector(1 downto 0);
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clk : in std_ulogic;
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lock : out std_ulogic;
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errorn : inout std_ulogic;
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wdogn : inout std_ulogic;
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address : out std_logic_vector(27 downto 0);
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data : inout std_logic_vector(31 downto 0);
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cb : inout std_logic_vector(7 downto 0);
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sdclk : out std_ulogic;
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sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
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sdwen : out std_ulogic; -- sdram write enable
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sdrasn : out std_ulogic; -- sdram ras
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sdcasn : out std_ulogic; -- sdram cas
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sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
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dsutx : out std_ulogic; -- DSU tx data / scanout
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dsurx : in std_ulogic; -- DSU rx data / scanin
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dsuen : in std_ulogic;
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dsubre : in std_ulogic; -- DSU break / scanen
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dsuact : out std_ulogic; -- DSU active / NT
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txd1 : out std_ulogic; -- UART1 tx data
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rxd1 : in std_ulogic; -- UART1 rx data
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txd2 : out std_ulogic; -- UART2 tx data
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rxd2 : in std_ulogic; -- UART2 rx data
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ramsn : out std_logic_vector (4 downto 0);
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ramoen : out std_logic_vector (4 downto 0);
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rwen : out std_logic_vector (3 downto 0);
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oen : out std_ulogic;
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writen : out std_ulogic;
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read : out std_ulogic;
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iosn : out std_ulogic;
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romsn : out std_logic_vector (1 downto 0);
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brdyn : in std_ulogic;
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bexcn : in std_ulogic;
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gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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i2c_scl : inout std_ulogic;
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i2c_sda : inout std_ulogic;
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spi_miso : in std_ulogic;
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spi_mosi : out std_ulogic;
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spi_sck : out std_ulogic;
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spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
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prom32 : in std_ulogic;
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spw_clksel : in std_logic_vector(1 downto 0);
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spw_clk : in std_ulogic;
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spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
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gtx_clk : in std_ulogic;
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erx_clk : in std_ulogic;
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erxd : in std_logic_vector(7 downto 0);
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erx_dv : in std_ulogic;
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etx_clk : in std_ulogic;
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etxd : out std_logic_vector(7 downto 0);
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etx_en : out std_ulogic;
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etx_er : out std_ulogic;
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erx_er : in std_ulogic;
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erx_col : in std_ulogic;
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erx_crs : in std_ulogic;
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emdint : in std_ulogic;
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emdio : inout std_logic;
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emdc : out std_ulogic;
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testen : in std_ulogic;
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trst : in std_ulogic;
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic
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);
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end;
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architecture rtl of leon3mp is
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signal lresetn : std_ulogic;
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signal lclksel : std_logic_vector (1 downto 0);
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signal lclk : std_ulogic;
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signal llock : std_ulogic;
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signal lerrorn : std_ulogic;
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signal laddress : std_logic_vector(27 downto 0);
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signal ldatain : std_logic_vector(31 downto 0);
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signal ldataout : std_logic_vector(31 downto 0);
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signal ldataen : std_logic_vector(31 downto 0);
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signal lcbin : std_logic_vector(7 downto 0);
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signal lcbout : std_logic_vector(7 downto 0);
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signal lcben : std_logic_vector(7 downto 0);
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signal lsdclk : std_ulogic;
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signal lsdcsn : std_logic_vector (1 downto 0);
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signal lsdwen : std_ulogic;
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signal lsdrasn : std_ulogic;
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signal lsdcasn : std_ulogic;
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signal lsddqm : std_logic_vector (3 downto 0);
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signal ldsutx : std_ulogic;
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signal ldsurx : std_ulogic;
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signal ldsuen : std_ulogic;
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signal ldsubre : std_ulogic;
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signal ldsuact : std_ulogic;
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signal ltxd1 : std_ulogic;
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signal lrxd1 : std_ulogic;
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signal ltxd2 : std_ulogic;
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signal lrxd2 : std_ulogic;
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signal lramsn : std_logic_vector (4 downto 0);
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signal lramoen : std_logic_vector (4 downto 0);
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signal lrwen : std_logic_vector (3 downto 0);
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signal loen : std_ulogic;
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signal lwriten : std_ulogic;
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signal lread : std_ulogic;
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signal liosn : std_ulogic;
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signal lromsn : std_logic_vector (1 downto 0);
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signal lbrdyn : std_ulogic;
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signal lbexcn : std_ulogic;
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signal lwdogn : std_ulogic;
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signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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signal li2c_sclout : std_ulogic;
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signal li2c_sclen : std_ulogic;
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signal li2c_sclin : std_ulogic;
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signal li2c_sdaout : std_ulogic;
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signal li2c_sdaen : std_ulogic;
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signal li2c_sdain : std_ulogic;
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signal lspi_miso : std_ulogic;
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signal lspi_mosi : std_ulogic;
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signal lspi_sck : std_ulogic;
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signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
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signal lprom32 : std_ulogic;
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signal lspw_clksel : std_logic_vector (1 downto 0);
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signal lspw_clk : std_ulogic;
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signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal lgtx_clk : std_ulogic;
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signal lerx_clk : std_ulogic;
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signal lerxd : std_logic_vector(7 downto 0);
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signal lerx_dv : std_ulogic;
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signal letx_clk : std_ulogic;
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signal letxd : std_logic_vector(7 downto 0);
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signal letx_en : std_ulogic;
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signal letx_er : std_ulogic;
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signal lerx_er : std_ulogic;
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signal lerx_col : std_ulogic;
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signal lerx_crs : std_ulogic;
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signal lemdint : std_ulogic;
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signal lemdioin : std_logic;
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signal lemdioout : std_logic;
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signal lemdioen : std_logic;
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signal lemdc : std_ulogic;
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signal ltesten : std_ulogic;
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signal ltrst : std_ulogic;
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signal ltck : std_ulogic;
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signal ltms : std_ulogic;
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signal ltdi : std_ulogic;
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signal ltdo : std_ulogic;
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signal ltdoen : std_ulogic;
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-- Use for ASIC
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--constant padvoltage : integer := x33v;
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--constant padlevel : integer := ttl;
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-- Use for FPGA
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constant padvoltage : integer := x18v;
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constant padlevel : integer := cmos;
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begin
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-- TODO: Move PAD options to 'xconfig'
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pads0 : entity work.pads
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generic map (
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padtech => CFG_PADTECH,
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padlevel => padlevel,
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padstrength => 10,
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jtag_padfilter => pullup,
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testen_padfilter => pulldown,
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resetn_padfilter => schmitt,
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clk_padfilter => 0,
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spw_padstrength => 12,
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jtag_padstrength => 6,
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uart_padstrength => 6,
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dsu_padstrength => 6,
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padvoltage => padvoltage,
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spw_input_type => CFG_SPW_INPUT,
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oepol => padoen_polarity(CFG_PADTECH)
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)
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port map (
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---------------------------
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--to chip boundary
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---------------------------
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resetn => resetn ,
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clksel => clksel ,
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clk => clk ,
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lock => lock ,
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errorn => errorn ,
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address => address ,
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data => data ,
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cb => cb ,
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sdclk => sdclk ,
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sdcsn => sdcsn ,
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sdwen => sdwen ,
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sdrasn => sdrasn ,
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sdcasn => sdcasn ,
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sddqm => sddqm ,
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dsutx => dsutx ,
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dsurx => dsurx ,
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dsuen => dsuen ,
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dsubre => dsubre ,
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dsuact => dsuact ,
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txd1 => txd1 ,
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rxd1 => rxd1 ,
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txd2 => txd2 ,
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rxd2 => rxd2 ,
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ramsn => ramsn ,
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ramoen => ramoen ,
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rwen => rwen ,
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oen => oen ,
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writen => writen ,
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read => read ,
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iosn => iosn ,
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romsn => romsn ,
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brdyn => brdyn ,
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bexcn => bexcn ,
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wdogn => wdogn ,
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gpio => gpio ,
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i2c_scl => i2c_scl ,
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i2c_sda => i2c_sda ,
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spi_miso => spi_miso ,
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spi_mosi => spi_mosi ,
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spi_sck => spi_sck ,
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spi_slvsel => spi_slvsel,
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prom32 => prom32 ,
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spw_clksel => spw_clksel,
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spw_clk => spw_clk ,
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spw_rxd => spw_rxd ,
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spw_rxs => spw_rxs ,
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spw_txd => spw_txd ,
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spw_txs => spw_txs ,
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gtx_clk => gtx_clk ,
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erx_clk => erx_clk ,
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erxd => erxd ,
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erx_dv => erx_dv ,
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etx_clk => etx_clk ,
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etxd => etxd ,
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etx_en => etx_en ,
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etx_er => etx_er ,
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erx_er => erx_er ,
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erx_col => erx_col ,
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erx_crs => erx_crs ,
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emdint => emdint ,
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emdio => emdio ,
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emdc => emdc ,
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testen => testen ,
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trst => trst ,
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tck => tck ,
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tms => tms ,
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tdi => tdi ,
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tdo => tdo ,
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------------------------- ---
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--to core
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----------------------------
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lresetn => lresetn ,
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lclksel => lclksel ,
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lclk => lclk ,
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llock => llock ,
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lerrorn => lerrorn ,
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laddress => laddress ,
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ldatain => ldatain ,
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ldataout => ldataout ,
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ldataen => ldataen ,
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lcbin => lcbin ,
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lcbout => lcbout ,
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lcben => lcben ,
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lsdclk => lsdclk ,
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lsdcsn => lsdcsn ,
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lsdwen => lsdwen ,
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lsdrasn => lsdrasn ,
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lsdcasn => lsdcasn ,
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lsddqm => lsddqm ,
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ldsutx => ldsutx ,
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ldsurx => ldsurx ,
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ldsuen => ldsuen ,
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ldsubre => ldsubre ,
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ldsuact => ldsuact ,
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ltxd1 => ltxd1 ,
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lrxd1 => lrxd1 ,
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ltxd2 => ltxd2 ,
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lrxd2 => lrxd2 ,
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lramsn => lramsn ,
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lramoen => lramoen ,
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lrwen => lrwen ,
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loen => loen ,
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lwriten => lwriten ,
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lread => lread ,
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liosn => liosn ,
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lromsn => lromsn ,
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lbrdyn => lbrdyn ,
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lbexcn => lbexcn ,
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lwdogn => lwdogn ,
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lgpioin => lgpioin ,
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lgpioout => lgpioout ,
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lgpioen => lgpioen ,
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li2c_sclout => li2c_sclout,
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li2c_sclen => li2c_sclen ,
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li2c_sclin => li2c_sclin ,
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li2c_sdaout => li2c_sdaout,
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li2c_sdaen => li2c_sdaen ,
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li2c_sdain => li2c_sdain ,
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lspi_miso => lspi_miso ,
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lspi_mosi => lspi_mosi ,
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lspi_sck => lspi_sck ,
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lspi_slvsel => lspi_slvsel,
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lprom32 => lprom32 ,
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lspw_clksel => lspw_clksel,
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lspw_clk => lspw_clk ,
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lspw_rxd => lspw_rxd ,
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lspw_rxs => lspw_rxs ,
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lspw_txd => lspw_txd ,
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lspw_txs => lspw_txs ,
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lgtx_clk => lgtx_clk ,
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lerx_clk => lerx_clk ,
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lerxd => lerxd ,
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lerx_dv => lerx_dv ,
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letx_clk => letx_clk ,
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letxd => letxd ,
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letx_en => letx_en ,
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letx_er => letx_er ,
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lerx_er => lerx_er ,
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lerx_col => lerx_col ,
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lerx_crs => lerx_crs ,
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lemdint => lemdint ,
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lemdioin => lemdioin ,
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lemdioout => lemdioout ,
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lemdioen => lemdioen ,
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lemdc => lemdc ,
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ltesten => ltesten ,
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ltrst => ltrst ,
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ltck => ltck ,
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ltms => ltms ,
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ltdi => ltdi ,
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ltdo => ltdo ,
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ltdoen => ltdoen
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);
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-- ASIC Core
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core0 : entity work.core
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generic map (
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fabtech => CFG_FABTECH,
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memtech => CFG_MEMTECH,
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padtech => CFG_PADTECH,
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clktech => CFG_CLKTECH,
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disas => CFG_DISAS,
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dbguart => CFG_DUART,
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pclow => CFG_PCLOW,
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scantest => CFG_SCAN,
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bscanen => CFG_BOUNDSCAN_EN,
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oepol => padoen_polarity(CFG_PADTECH)
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)
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port map (
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----------------------------
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-- ASIC Ports/Pads
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----------------------------
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resetn => lresetn ,
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clksel => lclksel ,
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clk => lclk ,
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lock => llock ,
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errorn => lerrorn ,
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address => laddress ,
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datain => ldatain ,
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dataout => ldataout ,
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dataen => ldataen ,
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cbin => lcbin ,
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cbout => lcbout ,
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cben => lcben ,
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sdclk => lsdclk ,
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sdcsn => lsdcsn ,
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sdwen => lsdwen ,
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sdrasn => lsdrasn ,
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sdcasn => lsdcasn ,
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sddqm => lsddqm ,
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dsutx => ldsutx ,
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dsurx => ldsurx ,
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dsuen => ldsuen ,
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dsubre => ldsubre ,
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dsuact => ldsuact ,
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txd1 => ltxd1 ,
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rxd1 => lrxd1 ,
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txd2 => ltxd2 ,
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rxd2 => lrxd2 ,
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ramsn => lramsn ,
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ramoen => lramoen ,
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rwen => lrwen ,
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oen => loen ,
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writen => lwriten ,
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read => lread ,
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iosn => liosn ,
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romsn => lromsn ,
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brdyn => lbrdyn ,
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bexcn => lbexcn ,
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wdogn => lwdogn ,
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gpioin => lgpioin ,
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gpioout => lgpioout ,
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gpioen => lgpioen ,
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i2c_sclout => li2c_sclout,
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i2c_sclen => li2c_sclen ,
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i2c_sclin => li2c_sclin ,
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i2c_sdaout => li2c_sdaout,
|
|
i2c_sdaen => li2c_sdaen ,
|
|
i2c_sdain => li2c_sdain ,
|
|
spi_miso => lspi_miso ,
|
|
spi_mosi => lspi_mosi ,
|
|
spi_sck => lspi_sck ,
|
|
spi_slvsel => lspi_slvsel,
|
|
prom32 => lprom32 ,
|
|
spw_clksel => lspw_clksel,
|
|
spw_clk => lspw_clk ,
|
|
spw_rxd => lspw_rxd ,
|
|
spw_rxs => lspw_rxs ,
|
|
spw_txd => lspw_txd ,
|
|
spw_txs => lspw_txs ,
|
|
gtx_clk => lgtx_clk ,
|
|
erx_clk => lerx_clk ,
|
|
erxd => lerxd ,
|
|
erx_dv => lerx_dv ,
|
|
etx_clk => letx_clk ,
|
|
etxd => letxd ,
|
|
etx_en => letx_en ,
|
|
etx_er => letx_er ,
|
|
erx_er => lerx_er ,
|
|
erx_col => lerx_col ,
|
|
erx_crs => lerx_crs ,
|
|
emdint => lemdint ,
|
|
emdioin => lemdioin ,
|
|
emdioout => lemdioout ,
|
|
emdioen => lemdioen ,
|
|
emdc => lemdc ,
|
|
testen => ltesten ,
|
|
trst => ltrst ,
|
|
tck => ltck ,
|
|
tms => ltms ,
|
|
tdi => ltdi ,
|
|
tdo => ltdo ,
|
|
tdoen => ltdoen ,
|
|
----------------------------
|
|
-- BSCAN
|
|
----------------------------
|
|
chain_tck => OPEN ,
|
|
chain_tckn => OPEN ,
|
|
chain_tdi => OPEN ,
|
|
chain_tdo => '0',
|
|
bsshft => OPEN ,
|
|
bscapt => OPEN ,
|
|
bsupdi => OPEN ,
|
|
bsupdo => OPEN ,
|
|
bsdrive => OPEN ,
|
|
bshighz => OPEN
|
|
);
|
|
|
|
-- BSCAN
|
|
-- TODO: ADD BSCAN
|
|
|
|
|
|
end;
|
|
|