ReonV/designs/leon3-digilent-nexys4ddr

This LEON design is tailored to the Digilent Nexys4-DDR board
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Simulation and synthesis
------------------------

The design currently supports synthesis with Xilinx Vivado (tested
with Vivado 2017.1).

The design currently supports simulation with modelsim 10.5a and riviera 2017.2

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

The on-board DDR2 memory can be interfaced through the Gaisler DDR2SPA
memory controller or the Xilinx MIG memory interface.

If enabled by the user, the design uses the Xilinx MIG memory
interface with an AHB-2.0 interface (experimental).  The MIG source
code cannot be distributed due to the prohibitive Xilinx license, so
the MIG must be re-generated with coregen before simulation and
synthesis can be done. Xilinx MIG interface will automatically be
generated when Vivado is launched.

To simulate using XSIM and run systest.c on the Leon design using the
memory controller from Xilinx use the make targets:

  make soft
  make vivado-launch

To simulate using ModelSim/Aldec and run systest.c on the Leon design using
the DDR2SPA memory controller:

  make soft
  make vsim - or - riviera
  make sim-launch - or riviera-launch

To simulate using Modelsim/Aldec and run systest.c on the Leon design using 
the memory controller from Xilinx use the make targets:

  make map_xilinx_7series_lib
  make sim (only required if Modelsim/Aldec is used as simulator)
  make mig_7series (only required if Xilinx MIG is enabled via xconfig)
  make soft
  make sim-launch

To simulate using Aldec Riviera use the following make targets:

  make map_xilinx_7series_lib
  make riviera
  make mig_7series (only required if Xilinx MIG is enabled via xconfig)
  make soft
  make riviera-launch

To synthesize the design, do

  make vivado (or make vivado-launch for the GUI flow)

Finally, to program the FPGA:
  
  make vivado-prog-fpga

When the DDR2SPA controller is enabled, the same flow can be followed, but there is no need to issue "make mig_7series".


Design specifics
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* The default configuration sets the system frequency to 70 MHz.

* The DDR2SPA controller can run up to 150 MHz. The default
  configuration assumes 140 MHz.  To enable the DDR2SPA controller,
  issue "make xconfig" and set the DDR2 SDRAM Controller tab to the
  following values:

- Enable power-on initialization:       Yes
- DDR clock is aligned to system clock: No
- Memory Frequency:                     140 MHz
- tRFC:                                 130 ns
- Column address bits:                  10
- Chip select bank size:                128 Mbyte
- Data width:                           16

* When enabled, the MIG controller runs at 70 MHz clock. The DDR2
  memory runs at 280 MHz.

* The AHB clock is generated by the MMCM module in the MIG
  controller, and can be controlled via Coregen. When the 
  MIG DDR2 controller isn't present the AHB clock is generated
  from CLKGEN, and can be controlled via xconfig

* In order to connect through the USB JTAG-interface run "grmon -digilent".
  It is also possible to connect through ethernet. "grmon -eth <ip addr>"

* System reset is mapped to the CPU RESET button

* LED 0/1 indicate USB-UART RX/TX activity. (Connected to Debug UART)

* LED 2 DSU Debug Mode

* LED 3 indicate processor in error mode

* LED 4 indicate the end of the calibration phase for the memory controller

* The application UART1 is unconnected. To enable it, uncomment the in/out
  pads for the apbuart and comment out the ahbuart pads.

* The JTAG DSU interface is enabled and accessible via the USB/JTAG port
  and USB/UART.
  Start grmon with -digilent to connect with USB/JTAG.

* The on-board SPI-Flash memory is interfaced through the Gaisler SPI
  memory controller, and it is mapped at address 0x0.  By default, the
  simulation assumes that the boot-code is read from the SPI-Flash.
  To enable it issue "make xconfig" and set the SPI Memory controller
  tab. The following configuration has been tested on hardware:

- Enable SD card support:              No
- Read instruction:                    0B
- Dummy byte:                          No
- Dual output:                         No
- Address offset:                      0
- Clock divisor for device clock:      2
- Clock divisor for alt. device clock: 2

The SPI Flash memory can be initialized, erased and written through GRMON:

grmon2> spim flash detect
  Got manufacturer ID 0x01 and device ID 0x2018
  Detected device: Spansion S25FL128S

grmon2> spim flash erase
  Erase successful!

grmon2> spim flash load <file name> (to load a file)

* The board supports 10/100 Mbit Ethernet.  The IP address of the
  Ethernet Debug Link interface can be changed by issuing in GRMON the
  following command:
 
  edcl <ip address>

  The default IP is 192.168.0.48

* When using the DDR2SPA controller, in order to calibrate the data
  delays connect through GRMON and run "ddr2delay scan" command:

grmon2> ddr2delay scan 
  DDR2 Delay calibration routine
  - Resetting delays
  - Trying read-delay 0 cycles
  Bits  15- 8: ---------------------------------------------------------------- -1
  Bits   7- 0: ---------------------------------------------------------------- -1
  - Trying read-delay 1 cycles
  Bits  15- 8: OOOOOOOOOOOOO-------------------OOOOOOOOOOOOO------------------- 6
  Bits   7- 0: OOOOOOOOOOO---------------------OOOOOOOOOOO--------------------- 5
  - Verifying
  - Calibration done


Finally, quit and enter again GRMON. After restarting GRMON, "info
sys" should report the correct memory configuration for the ddr2spa0
instance:

  using port /dev/ttyUSB1 @ 460800 baud
  GRLIB build version: 4151
  Detected frequency:  70 MHz
  
  Component                            Vendor
  LEON3 SPARC V8 Processor             Aeroflex Gaisler
  AHB Debug UART                       Aeroflex Gaisler
  JTAG Debug Link                      Aeroflex Gaisler
  GR Ethernet MAC                      Aeroflex Gaisler
  AHB/APB Bridge                       Aeroflex Gaisler
  LEON3 Debug Support Unit             Aeroflex Gaisler
  Single-port DDR2 controller          Aeroflex Gaisler
  SPI Memory Controller                Aeroflex Gaisler
  Generic UART                         Aeroflex Gaisler
  Multi-processor Interrupt Ctrl.      Aeroflex Gaisler
  Modular Timer Unit                   Aeroflex Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon2> info sys
  cpu0      Aeroflex Gaisler  LEON3 SPARC V8 Processor    
            AHB Master 0
  ahbuart0  Aeroflex Gaisler  AHB Debug UART    
            AHB Master 1
            APB: 80000700 - 80000800
            Baudrate 460800, AHB frequency 74.00 MHz
  ahbjtag0  Aeroflex Gaisler  JTAG Debug Link    
            AHB Master 2
  greth0    Aeroflex Gaisler  GR Ethernet MAC    
            AHB Master 3
            APB: 80000F00 - 80001000
            IRQ: 12
            edcl ip 192.168.0.48, buffer 2 kbyte
  apbmst0   Aeroflex Gaisler  AHB/APB Bridge    
            AHB: 80000000 - 80100000
  dsu0      Aeroflex Gaisler  LEON3 Debug Support Unit    
            AHB: 90000000 - A0000000
            AHB trace: 64 lines, 32-bit bus
            CPU0:  win 8, hwbp 2, itrace 64, V8 mul/div, lddel 1
                   stack pointer 0x47fffff0
                   icache 4 * 4 kB, 32 B/line e: %d lines, %d-bit bus
                   dcache 4 * 4 kB, 32 B/line e: %d lines, %d-bit bus
  ddr2spa0  Aeroflex Gaisler  Single-port DDR2 controller    
            AHB: 40000000 - 48000000
            AHB: FFF00100 - FFF00200
            16-bit DDR2 : 1 * 128 MB @ 0x40000000, 8 internal banks
            140 MHz, col 10, ref 7.8 us, trfc 135 ns
  spim0     Aeroflex Gaisler  SPI Memory Controller    
            AHB: FFF70000 - FFF70100
            AHB: 00000000 - 01000000
            IRQ: 7
            SPI memory device read command: 0x0b
  uart0     Aeroflex Gaisler  Generic UART    
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38381
  irqmp0    Aeroflex Gaisler  Multi-processor Interrupt Ctrl.    
            APB: 80000200 - 80000300
  gptimer0  Aeroflex Gaisler  Modular Timer Unit    
            APB: 80000300 - 80000400
            IRQ: 8
            8-bit scalar, 2 * 32-bit timers, divisor 74