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https://github.com/lcbcFoo/ReonV.git
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87 lines
2.7 KiB
Makefile
87 lines
2.7 KiB
Makefile
include .config
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GRLIB=../..
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TOP=leon3mp
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BOARD=gr-xc6s
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DESIGN=leon3-gr-xc6s
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TECHNOLOGY=spartan6
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
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UCF=leon3mp.ucf
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ifeq ("$(CONFIG_SPW_ENABLE)","y")
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UCF+=spacewire.ucf
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endif
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ifeq ("$(CONFIG_GRUSBHC_ENABLE)","y")
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UCF+=usb.ucf
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endif
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ifeq ("$(CONFIG_GRUSBDC_ENABLE)","y")
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UCF+=usb.ucf
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endif
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ifeq ("$(CONFIG_GRUSB_DCL)","y")
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UCF+=usb.ucf
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endif
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ifeq ("$(CONFIG_GRETH_GIGA)","y")
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UCF+=greth_gbit.ucf
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endif
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UCF_PLANAHEAD=$(UCF)
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QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
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EFFORT=high
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ISEMAPOPT=-timing
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XSTOPT=
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SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
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VHDLOPTSYNFILES= mig37/mig_37/user_design/rtl/iodrp_controller.vhd \
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mig37/mig_37/user_design/rtl/iodrp_mcb_controller.vhd \
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mig37/mig_37/user_design/rtl/mcb_raw_wrapper.vhd \
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mig37/mig_37/user_design/rtl/mcb_soft_calibration.vhd \
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mig37/mig_37/user_design/rtl/mcb_soft_calibration_top.vhd \
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mig37/mig_37/user_design/rtl/memc3_infrastructure.vhd \
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mig37/mig_37/user_design/rtl/memc3_wrapper.vhd \
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mig37/mig_37/user_design/rtl/mig_37.vhd \
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mig39/mig_39/user_design/rtl/iodrp_controller.vhd \
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mig39/mig_39/user_design/rtl/iodrp_mcb_controller.vhd \
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mig39/mig_39/user_design/rtl/mcb_raw_wrapper.vhd \
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mig39/mig_39/user_design/rtl/mcb_soft_calibration.vhd \
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mig39/mig_39/user_design/rtl/mcb_soft_calibration_top.vhd \
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mig39/mig_39/user_design/rtl/memc3_infrastructure.vhd \
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mig39/mig_39/user_design/rtl/memc3_wrapper.vhd \
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mig39/mig_39/user_design/rtl/mig_39.vhd \
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config.vhd svga2ch7301c.vhd ahbrom.vhd \
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ahb2mig_grxc6s_2p.vhd vga_clkgen.vhd leon3mp.vhd
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VHDLSIMFILES=testbench.vhd
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SIMTOP=testbench
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#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
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SDCFILE=default.sdc
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BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
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CLEAN=soft-clean migclean
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VCOMOPT=-explicit
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TECHLIBS = unisim secureip
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VSIMOPT= -t ps -novopt +notimingchecks -do $(GRLIB)/bin/runvsim.do $(SIMTOP)
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip cypress ihp gsi fmf spansion micron
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DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci ambatest ddr \
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leon4v0 l2cache gr1553b iommu ascs slink pwm \
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hcan
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FILEADD = MCB.vhd
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FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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################## project specific targets ##########################
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mig:
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cp -r grlib_mig/mig37 .
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coregen -b mig37/mig.xco -p mig37
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patch -p0 < grlib_mig/mig.diff
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mig39:
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cp -r grlib_mig/mig39 .
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coregen -b mig39/mig.xco -p mig39
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patch -p0 < grlib_mig/mig_patch.txt
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patch -p0 < grlib_mig/memc3_infrastructure_patch.txt
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patch -p0 < grlib_mig/mcb_soft_calibration_patch.txt
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migclean:
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-rm -rf mig37 mig39
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