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30 lines
1.3 KiB
Text
30 lines
1.3 KiB
Text
# Set the ULPI_CLK constraints
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#NET “usb_clk” TNM_NET = “usb_clk”;
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#TIMESPEC “TS_usb_clk” = PERIOD “usb_clk” 16.667 ns HIGH 50%;
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NET "usb_clk" PERIOD = 16.667 ns HIGH 50 %;
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#offset in constraints are calculated as follows.
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#clock frequency is 16.667ns
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#ULPI PHY output delay for output clock mode for ISP1504A is 3.8ns
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#onboard trace delay would be 1ns
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#input offset = (clock period - PHY outputdelay - trance delay)
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#with 1ns hold requirement for the PHY, considering 200ps clock jitter
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#OFFSET IN valid period would be 800ps.
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# Set the OFFSET IN delay as 12.167 ns with respect to ULPI CLK
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OFFSET = IN 12.167 ns VALID 12.967 ns BEFORE usb_clk RISING;
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# ULPI PHY setup time for output clock mode is 3ns in nom case
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# leaving 1ns for onboard trace delay.
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# OFFSET OUT = clock period - (PHY setup time + trace delay)
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# Set the OFFSET OUT delay as 12.667 ns with respect to ULPI_CLK
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OFFSET = OUT 12.667 ns AFTER usb_clk RISING;
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# Set MAX DELAY constraint on ULPI DIR pin
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NET "usb_dir" TNM = "usb_pin_grp";
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TIMESPEC TS_usb_dir = FROM "usb_pin_grp" TO PADS 4 ns;
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# Cross clock domain timing Constraints between ULPI Clock and AMBA clock
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NET "uclk" TNM_NET = "uclk";
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TIMESPEC "TS_clkm_usb_clk" = FROM "clkm" TO "uclk" 16 ns DATAPATHONLY;
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TIMESPEC "TS_usb_clk_clkm" = FROM "uclk" TO "clkm" 16 ns DATAPATHONLY;
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