ReonV/designs/leon3-xilinx-kc705

This design is tailored to the Xilinx Kintex-7 KC705 board

http://www.xilinx.com/kc705

Note: This design requires that the GRLIB_SIMULATOR variable is
correctly set. Please refer to the documentation in doc/grlib.pdf for
additional information.

Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.

Note: You must have Vivado 2017.1 in your path for the make targets to work.

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

Design specifics
----------------

* Synthesis should be done using Vivado 2017.1 or newer. For newer versions
  the MIG project may need to be updated.

* This design has GRFPU enabled by default. If your release doesn't contain
  GRFPU, it has to be disabled in order to build the design.

* The DDR3 controller is implemented with Xilinx MIG 7-Seriesand 
  runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz
  (DDR3-800).

* The AHB clock is generated by the MMCM module in the DDR3
  controller, and can be controlled via Vivado. When the 
  MIG DDR3 controller isn't present the AHB clock is generated
  from CLKGEN, and can be controlled via xconfig

* System reset is mapped to the EAST button
  (This is since the CPU RESET button pin is used for DDR VTP)

* DSU break is mapped to GPIO east button

* LED 0 indicates processor in debug mode

* LED 1 indicates processor in error mode, execution halted

* LED 2 indicates DDR3 PHY initialization done (Only valid when MIG is present)

* LED 3 indicates internal PLL has locked (Only valid when MIG isn't present)

* 16-bit flash prom can be read at address 0. It can be programmed
  with GRMON version 2.0.30-74 or later.

* The application UART1 is connected to the USB/RS232 connector

* The JTAG DSU interface is enabled and accesible via the JTAG port.
  Start grmon with -xilusb to connect.

Simulation and synthesis
------------------------

The design uses the Xilinx MIG memory interface with an AHB-2.0
interface. The MIG source code cannot be distributed due to the
prohibitive Xilinx license, so the MIG must be re-generated with 
Vivado before simulation and synthesis can be done.

Xilinx MIG interface will automatically be generated when 
Vivado is launched  

To simulate using XSIM and run systest.c on the Leon design using the memory 
controller from Xilinx use the make targets:

  make soft
  make vivado-launch

To simulate using Modelsim/Aldec and run systest.c on the Leon design using 
the memory controller from Xilinx use the make targets:

  make map_xilinx_7series_lib
  make sim
  make mig_7series
  make sim-launch

To simulate using Aldec Riviera WS flow use the following make targets:

  make riviera_ws               # creates riviera workspace
  make map_xilinx_7series_lib   # compiles and maps xilinx sim libs
  make mig_7series              # generates MIG IP and adds to riviera project
  make riviera                  # compile full project
  make riviera-launch           # launch simulation

To synthesize the design, do

  make vivado

and then use the programming tool:
  
  make vivado-prog-fpga

to program the FPGA.

After successfully programmed the FPGA the user might have to press
the 'EAST' button in order to successfully complete the calibration
process in the MIG. Led 1 and led 2 should be constant green if the
Calibration process has been successful.

If user tries to connect to the board and the MIG has not been
calibrated successfully 'grmon' will output: AMBA plug&play not found!

The MIG IP can be disabled deselecting the memory controller in 'xconfig'.
When no MIG is present in the system normal GRLIB flow can be used and no extra 
compile steps are needed. Also when when no MIG is present it 
is possible to control and set the system frequency via xconfig. 
Note that the system frequency can be modified via Vivado when the MIG is present
by modifying within specified limits for the MIG IP.

Compiling and launching modelsim when no memory controller and no ethernet interface
is present using Modelsim/Aldec simulator:

  make vsim
  make soft
  make vsim-launch

Simulation options
------------------

All options are set either by editing the testbench or specify/modify the generic 
default value when launching the simulator. For Modelsim use the option "-g" i.e.
to enable processor disassembly to console launch modelsim with the option: "-gdisas=1"

USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run time
(Option can now be controlled via 'make xconfig')

disas - Enable processor disassembly to console

Selecting External FLASH
------------------------

The KC705 ref design supports Linear BPI flash and Quad SPI flash. Due
to shared pins on the FPGA the two flash types can't co-exist in the design. 
Select flash type by enabling LEON2 memory controller for BPI flash or 
SPIMCTRL for Quad SPI flash in the configuration files for the design.

Quad SPI flash memory is controlled by the configuration mode settings on DIP switch 
SW13 position 5 (M0) and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the 
SPI flash memory device is selected. If mode pin M0 = 0, the Linear BPI flash memory 
device is selected.

Quad SPI flash is only supported by grmon2-2.0.56 or later

FPGA configuration
------------------

The BPI flash can be programmed by issuing the command make ise-prog-prom.

The configuration mode setting for SW13 should be M[2:0] = 010 and the full
SW13 should be:

     SW13-1     off
     SW13-2     off
     SW13-3     off
     SW13-4     on
     SW13-5     off

Output from GRMON
------------------

 grmon -xilusb
  
  GRMON2 LEON debug monitor v2.0.30-149-ga91ee12 internal version
  
  Copyright (C) 2012 Aeroflex Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  

Parsing -xilusb
Xilusb: Cable type/rev : 0x3 
 JTAG chain (1): xc7k325t 

Commands missing help:
 debug

  GRLIB build version: 4119
  Detected frequency:  100 MHz
  
  Component                            Vendor
  LEON4 SPARC V8 Processor             Aeroflex Gaisler
  AHB Debug UART                       Aeroflex Gaisler
  JTAG Debug Link                      Aeroflex Gaisler
  LEON2 Memory Controller              European Space Agency
  AHB/APB Bridge                       Aeroflex Gaisler
  LEON4 Debug Support Unit             Aeroflex Gaisler
  Single-port AHB SRAM module          Aeroflex Gaisler
  Unknown device                       Aeroflex Gaisler
  Single-port AHB SRAM module          Aeroflex Gaisler
  Generic UART                         Aeroflex Gaisler
  Multi-processor Interrupt Ctrl.      Aeroflex Gaisler
  Modular Timer Unit                   Aeroflex Gaisler
  AMBA Wrapper for OC I2C-master       Aeroflex Gaisler
  General Purpose I/O port             Aeroflex Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon2> info sys
  cpu0      Aeroflex Gaisler  LEON4 SPARC V8 Processor    
            AHB Master 0
  ahbuart0  Aeroflex Gaisler  AHB Debug UART    
            AHB Master 1
            APB: 80000700 - 80000800
            Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0  Aeroflex Gaisler  JTAG Debug Link    
            AHB Master 2
  mctrl0    European Space Agency  LEON2 Memory Controller    
            AHB: 00000000 - 20000000
            APB: 80000000 - 80000100
            16-bit prom @ 0x00000000
  apbmst0   Aeroflex Gaisler  AHB/APB Bridge    
            AHB: 80000000 - 80100000
  dsu0      Aeroflex Gaisler  LEON4 Debug Support Unit    
            AHB: 90000000 - A0000000
            AHB trace: 64 lines, 64-bit bus
            CPU0:  win 8, hwbp 2, itrace 64, V8 mul/div, srmmu, lddel 1, GRFPU
                   stack pointer 0x20000ff0
                   icache 2 * 4 kB, 16 B/line lru
                   dcache 2 * 4 kB, 16 B/line lru
  ahbram0   Aeroflex Gaisler  Single-port AHB SRAM module    
            AHB: 20000000 - 20100000
            32-bit static ram: 4 kB @ 0x20000000
  adev7     Aeroflex Gaisler  Unknown device    
            AHB: 40000000 - 48000000
            APB: 80000400 - 80000500
  ahbram1   Aeroflex Gaisler  Single-port AHB SRAM module    
            AHB: A0000000 - A0100000
            32-bit static ram: 4 kB @ 0xa0000000
  uart0     Aeroflex Gaisler  Generic UART    
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38343
  irqmp0    Aeroflex Gaisler  Multi-processor Interrupt Ctrl.    
            APB: 80000200 - 80000300
  gptimer0  Aeroflex Gaisler  Modular Timer Unit    
            APB: 80000300 - 80000400
            IRQ: 8
            8-bit scalar, 2 * 32-bit timers, divisor 100
  i2cmst0   Aeroflex Gaisler  AMBA Wrapper for OC I2C-master    
            APB: 80000800 - 80000900
            IRQ: 11
  gpio0     Aeroflex Gaisler  General Purpose I/O port    
            APB: 80000A00 - 80000B00
  
grmon2> load systest.exe
  40000000 .text                    112.2kB / 112.2kB   [===============>] 100%
  40020000 .data                    163.1kB / 163.1kB   [===============>] 100%
  Total size: 275.28kB (1.19Mbit/s)
  Entry point 0x40000000
  Image /home/ringhage/grlib_git/designs/leon4-xilinx-kc705/systest.exe loaded
  
grmon2> verify systest.exe
  40000000 .text                    112.2kB / 112.2kB   [===============>] 100%
  40020000 .data                    163.1kB / 163.1kB   [===============>] 100%
  Total size: 275.28kB (85.27kbit/s)
  Entry point 0x40000000
  Image of /home/ringhage/grlib_git/designs/leon4-xilinx-kc705/systest.exe verified without errors
  
grmon2>