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1081 lines
38 KiB
Text
1081 lines
38 KiB
Text
----------------------- Release 2017.2-b4193 ---------------------------
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2017-05-30 Enabled GRFPU as default in leon3-xilinx-kc705,
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leon3-xilinx-ml605 and leon3-xilinx-vc707 template designs.
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2017-05-29 Added variable GRLIB_VIVADO_SOURCE_MGMT_MODE to allow definition
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of the source_mgmt_mode variable in Vivado. If not set, the
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default setting of Vivado is used.
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2017-05-26 Updated Xilinx designs for Vivado 2017.1
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2017-05-12 AHBSTAT: Extend to optionally support filtering and logging of
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multiple errors.
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2017-05-12 GRPCI2: Update to DMA descriptor handling.
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Added data descriptors was not always detected by the running
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DMA. The channel descriptor is now updated to point to the next
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data descriptor when disabled via the APB interface.
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2017-05-08 LEON3/4: Bugfix for incorrect store address when MMU is enabled
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and TLB is disabled. Only affected designs using separate TLB
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with fast write option (TLB_TYPE= 2). The default value after
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reset for TLB is enabled and existing designs that keep the TLB
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enabled are not affected. This issue is present all LEON designs
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with TLB_TYPE = 2 since GRLIB build 2627.
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2017-05-05 LEON3/LEON4: Avoid breaking into debug mode on RETT
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instructions because this causes incorrect behavior when
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resuming.
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2017-05-03 scripts: Added file scriptgen_variable_values.tcl to pass
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environment variables to GRLIB scripts.
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2017-04-19 IRQMP system test: Fix race condition in irqtest()
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2017-04-10 GRLIB revision numbering changed from x.y.z to yyyy.q.
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2017-04-10 SDCTRL64: Change decoding of chip select and bank address
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to align with MCTRL and SDCTRL in 64-bit mode.
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2017-03-20 Update Ethernet Phy simulation model to simulate/check
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interface setup/hold/clock-to-out timing.
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2017-03-16 Add template design for Terasic Altera DSP Development Kit,
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Stratix V Edition (leon3-terasic-s5gs-dsp)
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2017-02-07 leon3-xilinx-zc702: AHB2AXI bridge in the Zynq template design
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has been replaced with AHB2AXI3B bridge.
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2017-02-07 Added template design for Digilent Anvyl board
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(leon3-digilent-anvyl) contributed by Dag Stroman.
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2017-02-02 APB3CTRL: Respond with AMBA ERROR on unmapped APB area
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2017-01-26 Updated Xilinx designs for Vivado 2016.4
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2017-01-20 scripts: Corrections made to allow Quartus to run in GUI
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mode and to allow separate generation of Microsemi scripts
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2016-12-30 GRCLKGATE: Move delay balancing to techmap layer. Clean up
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scan test support.
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2016-12-30 APB3CTRL: Add generic to hide plug'n'play area.
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2016-12-02 GUIDE: Add information about MMU aliasing to data cache
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snooping section.
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2016-11-21 LEON3: notag VHDL generic can no longer be used to disable
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tagged arithmetic and CASA.
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2016-11-21 Add system test documentation to GRLIB user's manual
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2016-11-10 AHBJTAG: Restructure code to avoid issues with Vivado.
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2016-11-09 Add 64-bit and 128-bit wide versions of ahbrom.
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2016-11-04 Allow configuring MMU page size for leon_dsu_stat_base
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subsystem.
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2016-11-02 GRPCI2: Add support for grlib_async_reset_enable and
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grlib_sync_reset_enable_all from GRLIB config package.
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2016-10-27 AHBJTAG: Add support for grlib_sync_reset_enable_all
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AHBROM: Add support for grlib_sync_reset_enable_all
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2016-10-21 AHBCTRL: Add fall-through BAR option to redirect
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unmapped areas to specific slave.
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2016-09-22 Remove leon3-terasic-sockit from release
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2016-09-16 leon3-minimal: Updated leon3mp.vhd and testbench.vhd to
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allow simulations to terminate.
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2016-09-10 LEON3: Support option for more aggressive RAM power saving
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This feature requires specific memory block behavior
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("read-hold"), and is enabled based on the
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techmap.syncram_readhold vector, currently disabled for all
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technologies.
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2016-09-10 LEON3: Instruction cache MMU and power-down improvement
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- Use MMU cacheability setting to enable/disable caching
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per page when MMU is enabled. Icache used cached generic or
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assumed always on previously when MMU enabled.
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- Support disabling the Icache memories when Icache is disabled.
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(non-trivial due to a corner case the cycle after enabling)
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2016-08-30 LEON3: Bugfix for DPBM functionality. Affects LEON3
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implementations with branch prediction enabled from release
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1.4.0 to 1.5.3 (problem introduced in GRLIB 2015-02-07),
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build b4154-b4173.
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2016-08-18 AHBCTRL: Allow overlapping areas when generic shadow /= 0
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2015-08-11 AHBROM: pipe=1 implementation is modified in order not to
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deassert HREADY when HSEL is low.
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2015-08-10 scripts: Replace parts of script generation infrastructure
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with Tcl based solution.
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2016-07-08 Updated Xilinx designs for Vivado 2016.2
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2016-07-03 APBCTRL: Add support for grlib_async_reset_enable.
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2016-07-03 AHBCTRL: Add support for grlib_async_reset_enable.
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2016-07-03 SPICTRL: Increase to revision 6. Add support for dual and
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quad SPI protocols. Rename 3-wire mode to 3-wire protocol.
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Add support for grlib_async_reset_enable.
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2016-07-02 SPI: Remove ssn member from gaisler.spi.spi_out_type.
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2016-06-13 MCTRL/SDMCTRL: Add support for grlib_sync_reset_enable_all.
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2016-05-17 Updated Xilinx designs for Vivado 2016.1
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2016-04-05 RGMII Adapter: Fixed RX Valid delay bug in RGMII adapter.
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Internal RX Valid signal was always set to '0' when delayed
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more than 2 clock cycles
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2016-03-31 Techmap: Prefix constants used to select transceiver type with
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TT_X for Xilinx and TT_M for Microsemi (GTX0 is not TT_XGTX0).
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2016-03-31 Add AHB2AXI - AHB to AXI bridge IP core.
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2016-03-24 LEON3/DSU3: Extend number of available bits in DSU time tag
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counter and make counter available via %ASR22 - %ASR23.
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2016-02-28 GRGPIO: IFLAG register was automatically cleared when the
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interrupt condition was removed. IFLAG was only set for one
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cycle when a interrupt was edge triggered.
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2016-01-27 SPI2AHB: pirq was missing from APB PnP information
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----------------------- Release 1.5.0-b4164 ----------------------------
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2016-01-21 leon3-digilent-atlys: Update design, allow systest simulation
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2016-01-21 leon3-gr-xc6s: Update UCF used with ISE13
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2016-01-15 Add support for GRLIB_SIMULATOR=Questa
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2016-01-09 L3STAT: stati signal missing from sensitivity list could give
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simulation mismatch.
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2016-01-08 Change script generation for Xilinx Vivado so that recent
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versions of Vivado use and generate a simulation file list
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with files in the correct order. Vivado 2014.1 reorders files
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incorrectly while later versions incorrectly re-orders files
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if source_mgmt_mode is set to prevent reordering(!). Current
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script leaves source_mgmt_mode at default (All) and produces
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correct file order with 2015.4. Vivado 2015.4 SIGSEVs during
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elaboration when using XSim. Latest working version for
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simulation with XSim (Vivado's built-in simulator) is 2013.4.
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2016-01-07 Fix xconfig and xgrlib issues after sourcing Vivado settings
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file by unsetting LD_LIBRARY_PATH.
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2016-01-07 Convert Basys3, Nexys4DDR, Nexys4, Nexys Video, AC701, KC705,
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and VC707 designs to Xilinx Vivado 2015.4.
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2016-01-04 Added template design for Digilent Basys3
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(leon3-digilent-basys3)
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2016-01-04 Added template design for Digilent Nexys Video
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(leon3-digilent-nexys-video)
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2016-01-04 LEON3: Make ics/dcs cache control register fields read-only in
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disabled state when respective cache not implemented.
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2015-12-18 LEON3: Perform 2-beat read burst for LDD when cache is
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disabled/bypassed.
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2015-12-18 L3STAT: AHB statistics was not available when core was
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implemented with dsuen = 0 and nextev = 0.
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2015-12-17 LEON3: Add dsnoop=7 option to implement DCache snooping with
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valid bits moved to registers and using only single-port RAMs
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for the tags.
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2015-12-16 GPTIMER: Changed to only decrement the prescaler when at least
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one timer is enabled.
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2015-12-03 LEON3: Add support for alternative window pointer extension
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from SPARC V8E.
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2015-12-01 LEON3/IRQMP: Add support for booting up from arbitrary (8b
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aligned) address, for monitoring error mode state of CPUs
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and to force specified CPU into error mode via the IRQ
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controller. Enabled via bootreg generic on IRQ controller.
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2015-11-30 AHBFILE: add designs/leon3-ahbfile. AHBFILE is a simulation-
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only debug communication link that connects using a file.
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Same protocol as AHBUART.
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2015-11-27 GPTIMER: Added support for Windowed Watchdog (WWD)
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2015-11-25 Added support for dual port APB-controller.
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2015-11-16 Upgrade Xilinx AC701, KC705 and VC707 template design to
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support Vivado 2015.3.
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2015-11-16 LEON3: Snooping implementations that used syncram_dp blocks
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(dsnoop=1,2,5 but not dsnoop=6) since LEON3v3 required the
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syncram_dp to provide write-through behavior, which was not
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guaranteed. This could result in snooping miss in a corner case.
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Modify the syncram_dp entity in the techmap layer to emulate
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this functionality when needed in syncram_dp, in the same way
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as for syncram_2p.
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2015-11-16 LEON3: Fix undriven signal used only in dsnoop=5 configuration.
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2015-11-08 planAhead: Allow to set planAhead Bitgen options via
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PLANAHEAD_BITGEN variable. Added via set_property
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{steps.bitgen.args.More Options} { PLANAHEAD_BITGEN }.
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2015-11-08 L3STAT: Workaround for Design Compiler elaboration error when
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nmax /= 0 and ncnt > nmax.
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2015-11-07 scripts: Display GRLIB env variables at script generation
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2015-11-02 LEON3: Support CASA also for LDDEL=2
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2015-10-27 LEON3: Add support for LEON REX (reduced instruction set)
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2015-10-07 Add support for 64 interrupt sources.
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Can be enabled via global grlib.config package.
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2015-10-07 LEON3: Fix asr17 value for DPBM field when branch
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prediction is set to always enabled (bp=1)
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2015-10-07 Enable make ise-prog-prom target for AC701, KC705 and VC707
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template designs.
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2015-10-05 LEON3: Fix for branch prediction i-cache fetch avoidance
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feature when used in combination with local instruction RAM.
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2015-10-05 LEON3: Instruction cache flush while executing from local
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instruction RAM (ILRAM) lead to wrong address being propagated
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to RAM.
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2015-09-23 Removed template designs for obsolete Cyclone(I) boards
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2015-09-23 Removed template designs for obsolete Virtex2 boards
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2015-09-21 Improved GHDL simulation script
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2015-09-18 GRDMAC: Implement timeout timer for condition descriptors.
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Add debug interface for internal buffer. Implement conditional
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trigger on input signal.
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2015-09-14 L3STAT: Update to revision 1, change to register layout and
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support for up to 64 counters.
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2015-08-27 Improved SYNCRAMBW techmap for UNISIM, IGLOO2 and RTG4
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2015-08-18 DPRC: Add operating mode with EDAC. Add interrupt support.
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2015-08-17 Include DMA controller (GRDMAC) in all releases
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2015-08-12 Extend IP core documentation with register reset values and
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access attribues.
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2015-05-11 leon3-digilent-nexys4ddr: Update to support Vivado 2015.2
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2015-06-22 APBUART: Add control register bit 15 that selects one or two
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stop bits.
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2015-06-21 Add script support for Mentor Graphics FormalPro (Linux only)
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2015-05-11 leon3-digilent-nexys4ddr: Update to support Vivado 2015.1
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----------------------- Release 1.4.1-b4156 ----------------------------
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2015-05-05 scripts: Skip secureip files in UNISIM when secureip is missing
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from TECHLIBS
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2015-05-05 leon3-terasic-sockit: Simulation support updates
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2015-05-05 SPICTRL: Descriptions for bit 15 in event and mask registers
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were missing.
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2015-05-04 leon3-xilinx-ml50x: Fix UCF file in default configuration
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2015-04-24 Add GRLIB_SUMULTOR=ALDEC_RWS option, see Riviera section in
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GRLIB user's manual (doc/grlib.pdf)
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2015-04-24 Remove GRLIB cache of vendor simulation libraries. Simulation
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libraries now need to be imported for each installation. See
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the installation section in doc/grlib.pdf for instructions.
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2015-04-23 Xilinx ML605/ML50x/ML510 designs: Update simulation flow
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2015-04-23 Unisim: Add make install- targets for Xilinx verilog libs
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2015-04-22 Remove script support and targets for Symphony-EDA Sonata
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2015-04-22 Fix naming used for Xilinx 7-series (series7 to 7series)
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2015-04-22 Xilinx VC707: Added missing pin property for SGMII interface
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2015-04-22 Update simulation flow for Xilinx AC701, KC705 and VC707 designs
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2015-04-20 Break out Virtex techmap from techmap/unisim
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2015-04-20 Added techmap/virtex5 for Virtex5 SERDES
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2015-04-20 Added SKIP_SIM_TECHLIBS setting to avoid build of libraries
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in tech/ to avoid collisions when using prebuilt libraries.
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2015-04-19 Updated Aldec Riviera-PRO project generation
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----------------------- Release 1.4.0-b4154 ----------------------------
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2015-04-10 Xilinx ML510 design: add support for second Ethernet core
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through SGMII connection to the PHY
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2015-04-10 Xilinx ML50x design: add support for alternative SGMII
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connection to the PHY
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2015-04-10 Added Xilinx GTP and GTX transceiver technology mappings to the
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SERDES component, enabling SGMII on Xilinx
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2015-04-10 Add L3STAT IP core (performance counters)
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2015-04-10 Add GRPCI2, remove GRPCI1.
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2015-04-08 ML501/ML50x: Updated to ISE 14.7
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2015-04-05 Remove designs/netcard
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2015-03-27 Xilinx VC707/AC701/KC705 designs: Updated to Vivado 2014.4.1
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2015-03-23 Added template design for Nexys4-DDR (leon3-digilent-nexys4ddr)
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2015-03-20 Added template design for TerASIC SoCKit (leon3-terasic-sockit)
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2015-03-11 GRFPU/GRFPU-lite netlists: Add netlists for Xilinx Virtex6,
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Xilinx 7-series and Altera Cyclone V, Startix IV, Stratix V.
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2015-02-26 SPIMCTRL: Disable (previously experimental) support for
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SD cards. SPIMCTRL now only support SPI Flash devices.
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2015-02-19 DSU3/AHBTRACE: Remove HIRQ(15:1) from trace buffer.
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2015-02-18 LEON3: Optimize timing to avoid slow path through nullify
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in mmu_dcache.
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2015-02-18 LEON3: Optimize timing for multi-way i-cache in FPGA
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2015-02-18 LEON3: Alias ASI 0x18 with 0x3, alias ASI 0x19 with 0x4
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2015-02-09 LEON3: Add support for iTB overflow detection.
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2015-02-09 LEON3/DSU3: Support filtering on LDST from alternate space
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0x80 - 0xFF
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2015-02-07 Added synchronous I/O test module (SYNCIOTEST)
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2015-02-07 LEON3: Add optional support to block i-cache fetch for misses
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caused by branch prediction,
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2015-02-07 LEON3: Support SPARC V8E partial WRPSR
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2015-02-07 GRGPIO: Add logical-and, -or, and -xor for DOUT, DIR, IMASK,
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and INPEN registers. Increase core version to 3.
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2015-02-07 GRGPIO: Add additional bypass mode, configurable reset values,
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optional interrupt flag register, optional input enable
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register and optional pulse functionality
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2015-02-07 SRMMU: SRMMU used fault type invalid address for translation
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errors and internal error for AMBA ERROR responses.
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Corrected to use FSR.FT=Translation error for AMBA ERROR
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reponses and other errors defined as translation errors in
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the V8 manual. MMU can no longer report FT=internal error.
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2015-02-07 SRMMU: FSR and FAR could only be overwritten by FT=internal
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error when FSR.FT=invalid address error. Changed so that all
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errors except translation errors may be overwritten.
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2015-02-07 LEON3: HLOCK could get lost after SPLIT/RETRY response
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2015-02-07 syncram256bw: Compile fix for Cadence
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2015-02-07 GPTIMER: Add support for external latch and clear vectors
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2015-02-07 report_device: Support using custom routine for writing to
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testmod
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2015-02-07 AHBJTAG: For ASIC, use both AHB and JTAG resets to reset jtagcom
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2015-02-07 AHBTRACE: add support for enable reset value from external
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signal
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2015-01-13 SRMMU: Add support for grlib_async_reset_enable
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2014-10-30 LEON3: Allow use of ASI 0x1C also without MMU implemented.
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2014-10-28 Include simple byte, hword, word and dword test as part of
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systest function base_test().
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2014-10-23 Xilinx VC707/AC701/KC705 designs: Updated to Vivado 2014.3
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2014-10-17 Add support for Xilinx dynamic partial reconfiguration. See
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doc/dprc/.
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2014-09-15 LEON3: Small logic optimization of D-cache snooping logic
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2014-09-12 AHBTRACE: Add AMBA performance counter outputs
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2014-09-10 Xilinx VC707/AC701/KC705 designs: Updated to Vivado 2014.2
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2014-09-08 LEON3: ASI 8 (user mode instruction fetch) access resulted in
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bus access also after MMU exceptions when MMU No Fault bit was
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set (NF=1). Changed behaviour so that bus access is prevented
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also when SU=0,NF=1.
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2014-09-08 KC705: Support for Quad SPI flash added
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2014-08-25 SDCTRL,SDCTRL64: Add missing checks that could cause minimum
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tRAS timings below what had been configured. Only impacts
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90 MHz or higher frequency SDRAM operation.
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2014-08-12 IRQMP: Add support for interrupt remapping
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2014-08-05 DSU3: Do not increment trace buffer time tag when DSU is
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disabled (dsui.enable LOW) unless timer is forced via reg i/f.
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2014-08-03 APBUART/DCOM_UART: Only transmit one stop bit
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2014-08-03 Added template design for Xilinx ZC702 Evaluation Kit
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2013-07-29 TECHMAP/syncram: Include test-mode bypass functionality
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only for technologies where it's explicitly enabled (via
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array in gencomp.vhd)
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2014-07-15 Moved declaration of memtest_vector to techmap.
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Implemented memory test signal propagation for AHBTRACE.
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Existing designs are unaffected by this change.
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2014-07-15 AHBTRACE: Support external time tag signal
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2014-07-08 LEON3/DSU3: include support for two-port instruction buffer
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|
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2014-07-01 DSU3: Allow filtering instruction trace buffer for LDA/STA
|
|
|
|
2014-07-01 DSU3: Include support for instruction trace buffer filtering
|
|
|
|
2014-06-29 LEON3: Add npasi VHDL generic that enables SPARC V8E
|
|
nonprivileged ASI access.
|
|
|
|
2014-06-17 GRGPRBANK: Support optional external reset and read vectors.
|
|
|
|
2014-05-19 syncram: Add self-checking feature to debug memory mapping
|
|
(enabled via grlib.config option)
|
|
|
|
2014-05-10 LEON3/LEON4: Disable ASI wrapping. ASI(7:5) must now be
|
|
zero to access existing ASIs.
|
|
|
|
2014-05-08 Added SGMII to GMII Ethernet bridge (lib/gaisler/greth/sgmii.vhd)
|
|
for use with GRETH_GBIT. Technology map currently supports
|
|
Altera. SGMII support is also available for Xilinx through
|
|
Xilinx's SGMII PHY Interface, see template designs for 7-series.
|
|
|
|
2014-05-05 DSU3: Add support for AHB trace buffer filtering, trace
|
|
force, force timer enable and wide AHB buses.
|
|
|
|
2014-05-02 Vivado flow updated to ver 2014.1
|
|
|
|
2014-04-30 GRETH_GBIT: Added SYNCREG for controlling transmit switch to
|
|
improve timing after place and route
|
|
|
|
2014-04-30 GRETH: EDCL MDIO statemachine will now be disabled by control
|
|
register bits edcldisable and disable duplex detection bits.
|
|
|
|
2014-04-30 GRETH: Corrected clock domain for TX reset
|
|
|
|
2014-04-30 RSTGEN: Added constraints to reset block to prevent synthesis
|
|
to merge signals
|
|
|
|
2014-04-30 KC705: Updated simulation enviroment for Ethernet
|
|
|
|
2014-04-30 RGMII: Make better use of GRLIB SYNREG for CDC and added
|
|
reset to output register
|
|
|
|
2014-04-30 XILINX-SERIES7: Fixed byte write in fast simulation mode
|
|
|
|
----------------------- Release 1.3.7-b4144 ----------------------------
|
|
|
|
2014-04-16 Change default assignment of GRLIB_SIMULATOR to ModelSim
|
|
|
|
2014-04-15 DDR3RAM sim model: Improve memory usage
|
|
|
|
2014-04-11 RGMII: First revision of documentation for the RGMII IP
|
|
|
|
2014-04-11 SAED32-TECHMAP: Fixed Bidir mapping and corrected erroneous
|
|
instantiation of technology memory.
|
|
|
|
2014-04-11 LEON3-ASIC: Fixed simulation for SAED32 technology library
|
|
and modified design to work with base_test and greth_test
|
|
in systest
|
|
|
|
2014-04-10 Xilinx techmap: Assign SIM_COLLISION_CHECK generic in techmap
|
|
layer instead of patching UNSIM sources.
|
|
|
|
2014-04-10 Disable install-unisim and install-secureip targets when
|
|
GRLIB_SIMULATOR is set to Xilinx.
|
|
|
|
2014-04-10 Updated PlanAhead script generation to allow ISim simulation
|
|
|
|
2014-04-08 Updated the leon3-digilent-xc7z020 design to working condition
|
|
|
|
2014-04-04 10/100Mbit mode fix for RGMII and SGMII on Xilinx designs
|
|
- Fixed 10/100Mbit mode in RGMII for ref designs KC705,
|
|
AC701 and GR-XC6
|
|
- Fixed 10/100Mbit mode in SGMII for ref designs VC707
|
|
|
|
2013-04-04 PlanAhead flow updated to improve overall timing
|
|
|
|
2013-04-04 GRETH/GRETH_GBIT updated to support unchanged clock speed for
|
|
lower bit rates
|
|
|
|
2013-03-25 Remove lib/openchip
|
|
|
|
2013-03-25 Add template design for Xilinx AC701 board (leon3-xilinx-ac701)
|
|
|
|
2013-03-21 Set Unisim pad delays to zero to match ISE simulation model
|
|
behavior.
|
|
|
|
2013-03-18 GPTIMER/GRTIMER: Merge GRTIMER functionality into GPTIMER.
|
|
|
|
2014-03-06 DSU3: Add dsu3_mb to allow AHB trace of second AHB bus
|
|
|
|
2014-03-05 LEON3v3: Rearranged and updated IP core documentation.
|
|
|
|
2014-03-05 LEON3v3: Removed fast snooping option from xconfig menus,
|
|
default to always on.
|
|
|
|
2014-03-05 LEON3v3: Added safeguard to generate error in simulation if FT
|
|
features are accidentally enabled on non-FT version of LEON3.
|
|
|
|
2014-03-01 LEON3v3: Improve performance for d-cache in frozen state by
|
|
only fetching missing data instead of full d-cache line.
|
|
|
|
2014-02-17 GPTIMER: Add WDOGDIS and WDOGNMI fields, see GRIP for details.
|
|
|
|
2014-02-16 systest: Add -qnoambapp option if LDFLAGS variable is
|
|
undefined. If -qnoambapp leads to errors then these can be
|
|
fixed by defining LDFLAGS or installing a recent BCC version.
|
|
|
|
2014-02-09 MUL32/DIV32: Add support for grlib_async_reset_enable.
|
|
|
|
2014-01-18 Update documentation to warn for use of -use_new_parser yes
|
|
with Xilinx XST.
|
|
|
|
2014-01-13 Remove planAhead make target, use only planahead.
|
|
|
|
2014-01-03 Added generic DDR1, DDR2, DDR3 SDRAM simulation models
|
|
under lib/gaisler/sim.vhd. Updated most template designs
|
|
to use new models.
|
|
|
|
----------------------- Release 1.3.4-b4140 ----------------------------
|
|
|
|
2013-12-19 Fixed Xilinx planAhead flow for Spartan6 designs
|
|
|
|
2013-12-19 Updated leon3-asic template design
|
|
|
|
2013-12-19 Added techmap for Synopsys 32/28nm Generic Library (saed32)
|
|
|
|
2013-12-18 Updated Xilinx VC707 and KC705 designs for Vivado 2013.3
|
|
|
|
2013-12-18 Added template design for TerASIC DE4 development board
|
|
(designs/leon3-terasic-de4)
|
|
|
|
2013-12-18 LEON3v3: Support grlib_sync_reset_enable_all from GRLIB config
|
|
package.
|
|
|
|
2013-11-27 Added template designs for Digilent Nexys3 and Nexys4 boards.
|
|
|
|
2013-11-13 AHBRAM: Add scan test support
|
|
|
|
2013-11-01 Reverted techmap for IDDR2 primitive in Xilinx SPARTAN-6 and
|
|
added extra option in techmap library for aligning data to
|
|
clock edge inside SPARTAN-6 IO
|
|
|
|
2013-11-01 GRETH: Chapter for CRC offloading updated since we do NOT
|
|
support CRC offloading for fragmented TCP and UDP packets
|
|
over IPv4
|
|
|
|
2013-11-01 Change DDR controllers to use dedicated in/out record type.
|
|
Move internal types to separate ddrintpkg package.
|
|
|
|
2013-10-31 AHBCTRL: Print ERROR responses when ahbtrace is enabled
|
|
|
|
2013-10-31 AHBJTAG: Add generic to select jtagcom implementation
|
|
|
|
2013-09-24 MMU: testin signal propagation missing for MMU syncrams
|
|
|
|
2013-09-23 Add workaround for Design Compiler bug (internal error during
|
|
elaboration) triggered by AHBRAM.
|
|
|
|
2013-09-06 Added template design for Altera CycloneV E Development kit
|
|
(designs/leon3-altera-c5ekit)
|
|
|
|
2013-09-06 Added async AHB-to-Avalon adapter for use with Altera DDR
|
|
memory controllers (AHB2AVL)
|
|
|
|
----------------------- Release 1.3.1-b4135 ----------------------------
|
|
|
|
2013-08-29 Fix bashisms in scripts target
|
|
|
|
2013-08-28 Add SRECs to XSim (Vivado) simulation fileset
|
|
|
|
2013-08-16 Corrected default value in clkgen for Xilinx Series 7
|
|
|
|
2013-08-16 leon3-gr-xc6s: Fix for Ethernet
|
|
- Script for correcting RGMII board timing
|
|
- Added instructions to README file for correcting board timing
|
|
|
|
2013-08-16 Updated Vivado Flow to only support version 2013.2 and newer
|
|
- Supported XILINX IP now generated via VIVADO
|
|
- Improved support for XSIM
|
|
Note: This will affect all XILINX Series 7 boards
|
|
|
|
2013-08-16 AHB2MIG for 7-series: support for VIVADO 2013.2
|
|
|
|
2013-08-16 SGMII: Updated SGMII to support VIVADO 2013.2
|
|
|
|
2013-08-16 RGMII: Re-design of to get better timing in 10/100Mbit mode
|
|
|
|
2013-08-16 AHBJTAG: Reimplement jtagcom with shift registers in TCK
|
|
domain to allow TCK clock rates faster than AHB clock.
|
|
|
|
2013-08-06 LEON3: Bring back support for cache freeze
|
|
|
|
2013-07-29 Replace sdram.srec and sram.srec with ram.srec. "make soft"
|
|
now creates ram.srec. External designs may need to be changed
|
|
to take this into consideration.
|
|
|
|
----------------------- Release 1.3.0-b4133 ----------------------------
|
|
|
|
2013-07-24 Fix ML605 template design reset issue.
|
|
|
|
2013-07-23 Re-arrange MIG files in Xilinx designs and make sure make
|
|
distclean removes all created files.
|
|
|
|
2013-07-12 Remove deprecated ahbmst2 core (use ahbmst or ahbdma instead)
|
|
|
|
2013-07-09 Update support for Aldec Riviera-PRO
|
|
|
|
2013-07-02 Rename generated quartus project to $(TOP)_quartus
|
|
|
|
2013-06-29 Remove deprecated DDR controllers (lib/gaisler/ddrv1)
|
|
|
|
2013-06-27 Several designs require that the GRLIB_SIMULATOR variable is
|
|
set correctly. See doc/grlib.pdf and the template design's
|
|
README.txt file.
|
|
|
|
2013-06-20 Update bitfiles for most template designs.
|
|
|
|
2013-06-19 LEON3: Upgrade to version 3, highlights:
|
|
- Updated data cache, fetch full cache line on read miss
|
|
- Writes to %ASR16, 17, 19 - 31 are now privileged
|
|
- Updates to documentation
|
|
Note: Requires upgrade to GRMON2 2.0.38 / GRMON 1.1.59
|
|
|
|
2013-06-10 Add script support for Aldec ALINT
|
|
|
|
2013-05-28 Add PRECISIONOPT env variable for Mentor Precision flow
|
|
|
|
2013-05-23 Updated interrupt assignments in template designs to
|
|
match with guidelines given in doc/guide.pdf.
|
|
|
|
2013-05-20 AHBJTAG: Improve TDO generation while shifting address/data
|
|
to allow JTAG speeds up to 1/3 of the AHB speed.
|
|
|
|
2013-05-17 AHBJTAG/TAP: Allow passing in inverted tck directly from top
|
|
level instead of generating internally (for ASIC only)
|
|
|
|
2013-05-15 AHBJTAG: Change sampling and synchronization of TCK/TDI into
|
|
AHB clock domain to simplify ASIC constraining.
|
|
|
|
2013-05-06 leon3-gr-xc6s: Change txclock delay to fix Ethernet stability
|
|
problems.
|
|
|
|
2013-05-05 Add install/remove-unimacro targets
|
|
|
|
2013-04-21 "make vsim" with ModelSim 10.2 caused endless compiles due
|
|
to use of vmake, which does not support new "flat" library
|
|
type. Fix by forcing use of "directory" library type.
|
|
|
|
2013-04-19 GRGPIO systest: Allow irq test of IO[0] if pirq /= 0.
|
|
|
|
2013-03-28 Updated support for Xilinx Vivado and planAhead flows
|
|
|
|
2013-03-28 UNISIM techmap: Re-arrange, drop use of BUFGDLL for Virtex-5
|
|
|
|
2013-03-28 AHB2MIG for 7-series: Support memories larger than 128 MiB
|
|
|
|
2013-03-27 ML510 designs: Fix swapped chip-selects for DDR2 DIMM1
|
|
|
|
2013-03-25 Move AG PCI files into, and under, lib/gaisler/pci
|
|
|
|
2013-03-24 Fix swapped UART pins in SP605, KC705 and VC707 template
|
|
designs.
|
|
|
|
2013-03-19 GRETH systest: Do not test EDCL if EDCL disabled on reset.
|
|
|
|
2013-03-18 Add design contributed by Joris van Rantwijk for Digilent Atlys
|
|
board (leon3-digilent-atlys).
|
|
|
|
2013-03-13 Add grlib_sync_reset_enable_all option to GRLIB configuration
|
|
package that enables reset of all registers in IP cores that
|
|
support this functionality. See GRLIB Configuration package
|
|
section in grlib.pdf for additional information.
|
|
|
|
2013-03-08 AHBRAM: Allow values for kbytes larger than 512
|
|
Add larger size choices and expose pipe generic in xconfig
|
|
|
|
2013-02-19 Netlist search path was not correctly set for Spartan-3A-DSP
|
|
|
|
2013-02-11 SPICTRL: added support for external control - ignoring samples
|
|
|
|
2013-02-01 Netlists were not automatically copied to template designs
|
|
for CYCLONEIV-E technology.
|
|
|
|
----------------------- Release 1.2.2-b4123 ----------------------------
|
|
|
|
2013-01-31 Fixed Makefile error that prevented script generation for
|
|
Xilinx PlanAhead when MIG DDR2 controller was enabled in design.
|
|
|
|
----------------------- Release 1.2.1-b4122 ----------------------------
|
|
|
|
2013-01-15 Fixed soft calibration error for MIG39 in SPARTAN6 designs
|
|
|
|
2013-01-15 TECHMAP: Add support for SPARTAN-6 LVDS IOs
|
|
|
|
2013-01-15 leon3-gr-xc6s: Added clock deskew PLL to improve USB HOST timing
|
|
|
|
2013-01-15 Made GRLIB RGMII block technology independent
|
|
|
|
2013-01-15 Corrected erroneous instantiation of mig37 in ML605 design
|
|
|
|
----------------------- Release 1.2.0-b4121 ----------------------------
|
|
|
|
2012-12-20 Added ISE14.3 and PlanAhead support for Virtex 6 and Spartan 6
|
|
template designs.
|
|
|
|
2012-12-19 DDRSPA: Add phy implementation config VHDL generic (phyiconf)
|
|
|
|
2012-12-17 GRETH: Support larger frames (maxsize VHDL generic added)
|
|
|
|
2012-12-16 Added (experimental) support for Zynq-7000 and ZedBoard
|
|
(leon3-digilent-xc7z020).
|
|
|
|
2012-12-16 Added support for Xilinx VC707 and KC705 development kits
|
|
(leon3-xilinx-vc707 and leon3-xilinx-kc705)
|
|
|
|
2012-12-16 Added support for Xilinx Vivado flow
|
|
|
|
2012-12-16 Added support for Xilinx 7-series FPGAs (Virtex, Kintex, Artix)
|
|
|
|
2012-12-16 LEON: Fix possible pipeline hang after two consecutive DIV
|
|
operations. Bad sequence is not generated by compilers.
|
|
|
|
2012-12-14 leon3-gr-xc6s: Remove USBDC* from template design
|
|
|
|
2012-12-10 PCIPADS: Allow to select voltage and level via VHDL generics
|
|
|
|
2012-12-10 GRGPIO: Add capability register and increase core revision to 2
|
|
|
|
2012-12-07 DDRSPA: Fix reset delay bug in controller when pwron=0
|
|
|
|
2012-11-28 SPICTRL: Use testoen to control direction in test mode
|
|
|
|
2012-11-28 GRETH: Use testoen to control direction of mdio in test mode
|
|
|
|
2012-11-19 GRGPIO: Use testoen to control direction in test mode.
|
|
|
|
2012-11-17 Added AMBA test framework documentation to configuration guide
|
|
|
|
2012-11-17 Added option to select predefined example processor
|
|
configurations in xconfig.
|
|
|
|
2012-11-15 JTAG: Add oepol generic to control polarity of tdoen signal
|
|
Connect tdoen signal in the leon3-asic example design
|
|
|
|
2012-11-13 Added PWM Generator (GRPWM) to COM and FT distributions
|
|
|
|
2012-11-13 Added memory scrubber (MEMSCRUB) to FT distributions
|
|
|
|
2012-11-06 Remove HCACHE signal from AMBA records. This change may break
|
|
existing external IP cores.
|
|
|
|
2012-10-29 Added NAND Flash Memory Controller (NANDFCTRL) IP core
|
|
(to COM and FT releases).
|
|
|
|
2012-10-24 Makefile: added DESIGNER_LAYOUT_OPT to override all Designer
|
|
layout options.
|
|
|
|
2012-10-22 Added disable during scan test handling to syncram techmap.
|
|
Distribute testin vector for syncrams in AMBA records.
|
|
Updated GRLIB documentation on scan test support.
|
|
|
|
2012-10-15 Added LEON/GRLIB design and configuration guide (doc/guide.pdf)
|
|
|
|
2012-10-13 Remove ATACTRL
|
|
|
|
2012-10-12 LEON/SRMMU: Allow 64 TLB entries (for each TLB)
|
|
|
|
2012-10-12 Update GRLIB config package with grlib_config_array constant.
|
|
All local copies of the global configuration package needs to
|
|
be updated. All cores that make use of grlib_debug_* constants
|
|
need to be changed to use grlib_config_array(grlib_debug_*).
|
|
|
|
2012-10-11 LEON: Update IP core doc. regarding types of bus accesses
|
|
performed by the processors.
|
|
|
|
2012-10-03 DDRSPA,DDR2SPA: Add hooks for scan test support
|
|
|
|
2012-09-30 Update Aldec riviera targets to work with current versions.
|
|
|
|
2012-09-27 LEON3: Part of partially filled I-cache line could get
|
|
incorrectly marked as valid when executing branch
|
|
instruction with I-cache frozen and branch prediction
|
|
enabled. Does not affect LEON3FT.
|
|
|
|
2012-09-26 AHBRAM: Fix bug in wait state generation when pipe=1
|
|
|
|
2012-09-25 GRETH: Add generic to extend MDIO output hold time to more
|
|
than one AMBA cycle.
|
|
|
|
2012-09-25 GRCLKGATE: Add optional extra input for ungating all clocks
|
|
|
|
2012-09-25 GRCLKGATE: Propagate master reset asynchronously into gated
|
|
resets by logical AND:ing.
|
|
|
|
2012-09-24 Added IOMMU (GRIOMMU) to LEON4 relases.
|
|
|
|
2012-09-23 Removed CoreMP7 to GRLIB bridge and design.
|
|
|
|
2012-09-23 Removed WildCard design and WILD2AHB core.
|
|
|
|
2012-09-23 Removed HAPS files.
|
|
|
|
2012-09-11 AHBCTRL/AHBCTRL_MB: Treat HLOCK as coupled to specific access
|
|
to prevent HMASTLOCK assertion for normal accesses that receive
|
|
a SPLIT/RETRY response.
|
|
|
|
2012-09-06 Use VERILOGSYNFILES in script generation for XST and Synplify.
|
|
|
|
2012-09-06 Remove basic_passthru design
|
|
|
|
2012-09-06 Remove unmaintained designs leon3-ge-hpe-mini, -lattice and
|
|
leon3-ge-hpe-midi-ep2s180. Also removed libraries and cores
|
|
that were only used in these designs. Vendor and device IDs
|
|
are kept and files can manually be copied from older GRLIB
|
|
releases.
|
|
|
|
2012-08-24 SPICTRL: Core would generate one extra SCK cycle after
|
|
last word in queue for FACT = 1 and CPHA = 1.
|
|
|
|
2012-08-24 SPICTRL: Fix transmit queue race condition introduced in
|
|
1.1.0-b4108 that could result in corrupted transmit data.
|
|
|
|
2012-07-20 GRGPIO: irqgen=2,3,4 led to all irqmap registers getting
|
|
the same value on writes.
|
|
|
|
2012-07-11 I-cache flush via ASI 0x10 was a no-op for systems
|
|
implemented without MMU.
|
|
|
|
2012-06-261 DDRSPA,DDR2SPA: Move reset delay from phy to controller.
|
|
|
|
2012-06-151 DDRSPA,DDR2SPA: Remove the internal fast generic, use read
|
|
counters to get correct behavior for all speed ratios with the
|
|
same controller.
|
|
|
|
2012-05-10 DDRSPA,DDR2SPA: Moved ddr2spa and ddrspa components into their
|
|
own package ddrpkg. Make older versions of ddr controllers
|
|
available again under ddrv1 directory.
|
|
|
|
DDRSPA: Re-implemented to use the same structure as DDR2SPA.
|
|
DDRSPA: Add support for control signal timing up to DDR400.
|
|
|
|
2012-04-30 SPIMCTRL: Allow user to specify address offset for SPI device.
|
|
|
|
2012-04-25 leon3-gr-xc6: RGMII interface did not work with 10/100 MAC.
|
|
|
|
2012-04-24 leon3-xilinx-sp601: USB/UART had swapped RX/TX signals.
|
|
|
|
2012-04-12 Merged Xilinx ML505 - ML509 template designs into the design
|
|
leon3-xilinx-ml50x and added option to use the DDR2 MIG.
|
|
|
|
2012-04-11 Added template design for TerASIC DE0-Nano board
|
|
(leon3-terasic-de0-nano)
|
|
|
|
2012-03-19 Automatically perform "vsim-fix" when generating ModelSim
|
|
scripts to avoid issues with ':' in paths in Cygwin.
|
|
|
|
2012-03-05 GRACECTRL: Emulate 16-bit mode for 8-bit MPU interface.
|
|
Enable core for Xilinx ML605 and SP605 template designs.
|
|
|
|
2012-02-28 LEON3/4: Corrected documentation on cache flush ASIs.
|
|
|
|
----------------------- Release 1.1.0-b4113 ----------------------------
|
|
|
|
2012-01-18 Added template design for ZTEX USB-FPGA Module 1.15
|
|
(leon3-ztex-ufm-115). Renamed leon3-ztex-ufm-xc6slx25 to
|
|
leon3-ztex-ufm-111.
|
|
|
|
2012-01-10 Moved I2C and SPI cores to separate directories.
|
|
|
|
----------------------- Release 1.1.0-b4112 ----------------------------
|
|
|
|
2012-01-02 Added template design for Xilinx SP605 board
|
|
|
|
2011-12-29 Added template design for ZTEX USB-FPGA Module 1.11
|
|
(leon3-ztex-ufm-xc6slx25)
|
|
|
|
2011-12-28 Added SPI to AHB bridge (SPI2AHB) core
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----------------------- Release 1.1.0-b4111 ----------------------------
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2011-12-19 Added RGMII interface for GR-XC6S-LX75 board.
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2011-11-29 Work-around for Xilinx SecureIP compilation bug
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2011-11-29 Added MIG wrapper to a few additional template designs
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2011-11-28 Added support for Xilinx ISIM simulator.
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2011-11-18 Improved Actel Libero script generation
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2011-10-14 MMU system test software: Do not use %local register in leaf
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function. Could lead to test freeze with GCC 4.4.2.
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2011-10-06 DDR2SPA: Added support for registered SDRAM, and read-only
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tech field to DDR2CFG2 register. Increased core revision to 1
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in PnP entry.
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2011-09-29 SPICTRL: User was allowed to start a new transfer before SCK
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had transitioned to idle state. If a transfer was started
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early this could affect the clock phase for CPHA = 0.
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2011-09-26 Removed script support for early versions of eTools
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2011-09-26 Updated SPICTRL to rev 5 adding SCK filtering in slave mode
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2011-09-18 Added "Extending the xconfig GUI configuration" section to
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GRLIB User's Manual (grlib.pdf).
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2011-09-18 Added I2C to AHB bridge (I2C2AHB) core
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2011-09-06 AHBCTRL: Update memory map intersection checks and clarify
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in documentation that the AHB I/O area can be placed within
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a slave memory area
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2011-08-06 Enable 16-bit FLASH interface in leon3-nuhorizon design
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2011-07-06 I2CMST: Added option to use dynamic filter
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----------------------- Release 1.1.0-b4108 ----------------------------
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2011-06-15 Added DDR2 MIG wrapper for template design for
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Xilinx SP601 Spartan6 board.
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2011-06-13 Added template design for new Pender Spartan-6 board,
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including a wrapper for Xilinx MIG 16-bit DDR2 controller.
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2011-06-13 Added template designs for Xilinx ML605 board, including
|
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a wrapper for Xilinx MIG 64-bit DDR3 controller.
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2011-06-01 Added template design for Altera DE2 board, including
|
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16-bit SDRAM controller.
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2011-05-18 SPICTRL: Allow use of SYNCRAM_2P for buffers
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2011-04-12 Expanded section "9. Extending GRLIB" of GRLIB User's Manual
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2011-03-17 Added AHBTRACE_MMB capable of multi-bus tracing.
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2011-01-31 GRFPU-lite netlists for Altera could not be synthesized
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2011-01-13 SPICTRL: 3-wire transfer direction order can now be configured
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2011-01-09 Added template design for BeMicro SDK (leon3-arrow-bemicro-sdk)
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2011-01-04 Hynix DDR2 model, fix spurious error messages in simulation
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|
|
|
----------------------- Release 1.1.0-b4105 ----------------------------
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2010-11-29 DDR2SPA: Fast acknowlege on read was one cycle too early
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2010-11-22 DDR2SPA: Fix data selection for AHB buses wider than 2xDDR
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2010-11-17 DDR2SPA: Write mode register correctly based on CAS/TWR settings
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|
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2010-11-15 DDR2SPA: Add bigmem generic to enable >1GB RAM bank support
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|
|
|
2010-11-16 APBUART: Set number of scaler bits via VHDL generic
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|
|
|
2010-11-15 DDR2SPA: Separate reset generation for AHB/DDR clock domains
|
|
|
|
2010-11-12 GPTIMER: Allow external watchdog enable/disable.
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|
|
|
----------------------- Release 1.1.0-b4104 ----------------------------
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2010-10-29 Added design for TerASIC Altera Cyclone-IV DE2-115 board
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|
|
|
2010-10-29 Improved flow for Quartus-10
|
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|
|
2010-10-14 DDR2SPA: Reimplement DDR2 controller to merge all data sizes.
|
|
|
|
----------------------- Release 1.1.0-b4102 ----------------------------
|
|
|
|
2010-10-12 Support for Xilinx ISE12 flow.
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|
|
|
2010-10-01 Improved generation of Actel Libero project file to avoid
|
|
large amount of bogus warnings.
|
|
|
|
2010-09-23 DDR2SPA: Support single-ended DQS for Virtex4-6
|
|
|
|
2010-09-12 GPTIMER: IP field in timer control register is now write-clear
|
|
|
|
2010-08-09 GRGPIO: Add generic to specify the first interrupt line the core
|
|
should drive. Add support to dynamically specify the interrupt
|
|
line to use for each GPIO line.
|
|
|
|
2010-06-28 Added Testbench framework for PCI.
|
|
|
|
2010-06-28 PCI_TARGET: Added support for PCI bus in big-little mode
|
|
and support for byte and half word PCI accesses.
|
|
|
|
2010-06-07 I2CMST/I2CSLV: Added generic that adjusts low-pass filter
|
|
|
|
2010-05-19 AHBJTAG: Use bit 32 in read data to indicate if AHB access has
|
|
finished. Increased core version to 1.
|
|
|
|
2010-05-10 SPICTRL: Extended system test with test that uses an external
|
|
simulation device. Function now has one additional argument.
|
|
|
|
2010-05-06 XST: Remove -read_cores yes from XST script generation as yes
|
|
is the default read_cores setting. This allows specifying
|
|
-read_cores yes, no or optimize via the XSTOPT variable.
|
|
|
|
2010-05-05 FPU: GRFPU and GRFPU-lite netlists in both LEON3 and LEON4
|
|
versions are now available for Cyclone2, Cyclone3, Stratix2,
|
|
Stratix3, Spartan3, Virtex2, Virtex4 and Virtex5.
|
|
|
|
2010-05-05 FPU: Always use FPU netlists in distributions lacking FPU
|
|
source code.
|
|
|
|
2010-05-05 FPU: Use EDIF netlists for FPU netlist synthesis on Xilinx
|
|
|
|
2010-03-21 Improved input data filtering in serial DSU link (DCOM_UART).
|
|
|
|
2010-02-15 Added template design for Xilinx SP601 Spartan6 board
|
|
|
|
2010-02-01 Support for 64- and 128-bit AHB buses
|
|
|