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68 lines
2.2 KiB
VHDL
68 lines
2.2 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: eth_rstgen
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-- File: eth_rstgen.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Reset generation with glitch filter
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity eth_rstgen is
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generic (acthigh : integer := 0);
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port (
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rstin : in std_ulogic;
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clk : in std_ulogic;
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clklock : in std_ulogic;
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rstout : out std_ulogic;
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rstoutraw : out std_ulogic
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);
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end;
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architecture rtl of eth_rstgen is
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signal r : std_logic_vector(4 downto 0);
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signal rst : std_ulogic;
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attribute equivalent_register_removal : string;
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attribute keep : string;
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attribute equivalent_register_removal of r : signal is "no";
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attribute equivalent_register_removal of rst : signal is "no";
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attribute keep of r : signal is "true";
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attribute keep of rst : signal is "true";
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begin
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rst <= not rstin when acthigh = 1 else rstin;
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rstoutraw <= rst;
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reg1 : process (clk, rst) begin
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if rising_edge(clk) then
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r <= r(3 downto 0) & clklock;
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rstout <= r(4) and r(3) and r(2);
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end if;
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if rst = '0' then r <= "00000"; rstout <= '0'; end if;
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end process;
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end;
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