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219 lines
7 KiB
VHDL
219 lines
7 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: div32
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-- File: div32.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: This unit implemets a divide unit to execute 64-bit by 32-bit
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-- division. The divider leaves no remainder.
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-- Overflow detection is performed according to the
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-- SPARC V8 manual, method B (page 116)
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-- Division is made using the non-restoring algorithm,
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-- and takes 36 clocks. The operands must be stable during
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-- the calculations. The result is available one clock after
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-- the ready signal is asserted.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.config_types.all;
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use grlib.config.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.arith.all;
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entity div32 is
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generic (scantest : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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holdn : in std_ulogic;
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divi : in div32_in_type;
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divo : out div32_out_type;
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testen : in std_ulogic := '0';
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testrst : in std_ulogic := '1'
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);
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end;
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architecture rtl of div32 is
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type div_regtype is record
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x : std_logic_vector(64 downto 0);
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state : std_logic_vector(2 downto 0);
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zero : std_logic;
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zero2 : std_logic;
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qcorr : std_logic;
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zcorr : std_logic;
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qzero : std_logic;
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qmsb : std_logic;
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ovf : std_logic;
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neg : std_logic;
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cnt : std_logic_vector(4 downto 0);
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end record;
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constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
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constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
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constant RRES : div_regtype := (
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x => (others => '0'),
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state => (others => '0'),
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zero => '0',
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zero2 => '0',
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qcorr => '0',
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zcorr => '0',
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qzero => '0',
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qmsb => '0',
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ovf => '0',
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neg => '0',
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cnt => (others => '0'));
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signal arst : std_ulogic;
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signal r, rin : div_regtype;
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signal addin1, addin2, addout: std_logic_vector(32 downto 0);
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signal addsub : std_logic;
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begin
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arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else
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rst when ASYNC_RESET else
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'1';
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divcomb : process (r, rst, divi, addout)
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variable v : div_regtype;
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variable vready, vnready : std_logic;
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variable vaddin1, vaddin2 : std_logic_vector(32 downto 0);
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variable vaddsub, ymsb : std_logic;
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constant zero33: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
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begin
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vready := '0'; vnready := '0'; v := r;
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if addout = zero33 then v.zero := '1'; else v.zero := '0'; end if;
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vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
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vaddsub := not (divi.op2(32) xor r.x(64));
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v.zero2 := r.zero;
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case r.state is
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when "000" =>
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v.cnt := "00000";
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if (divi.start = '1') then
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v.x(64) := divi.y(32); v.state := "001";
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end if;
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when "001" =>
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v.x := divi.y & divi.op1(31 downto 0);
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v.neg := divi.op2(32) xor divi.y(32);
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if divi.signed = '1' then
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vaddin1 := divi.y(31 downto 0) & divi.op1(31);
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v.ovf := not (addout(32) xor divi.y(32));
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else
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vaddin1 := divi.y; vaddsub := '1';
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v.ovf := not addout(32);
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end if;
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v.state := "010";
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when "010" =>
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if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = zero33) then v.ovf := '0'; end if;
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v.qmsb := vaddsub; v.qzero := '1';
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v.x(64 downto 32) := addout;
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v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
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v.state := "011"; v.zcorr := v.zero;
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v.cnt := r.cnt + 1;
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when "011" =>
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v.qzero := r.qzero and (vaddsub xor r.qmsb);
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v.zcorr := r.zcorr or v.zero;
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v.x(64 downto 32) := addout;
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v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
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if (r.cnt = "11111") then v.state := "100"; vnready := '1';
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else v.cnt := r.cnt + 1; end if;
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v.qcorr := v.x(64) xor divi.y(32);
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when "100" =>
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vaddin1 := r.x(64 downto 32);
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v.state := "101";
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when others =>
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vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
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vaddin2 := (others => '0'); vaddin2(0) := '1';
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vaddsub := (not r.neg);-- or (r.zcorr and not r.qcorr);
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if ((r.qcorr = '1') or (r.zero = '1')) and (r.zero2 = '0') then
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if (r.zero = '1') and ((r.qcorr = '0') and (r.zcorr = '1')) then
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vaddsub := r.neg; v.qzero := '0';
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end if;
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v.x(64 downto 32) := addout;
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else
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v.x(64 downto 32) := vaddin1; v.qzero := '0';
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end if;
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if (r.ovf = '1') then
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v.qzero := '0';
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v.x(63 downto 32) := (others => '1');
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if divi.signed = '1' then
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if r.neg = '1' then v.x(62 downto 32) := (others => '0');
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else v.x(63) := '0'; end if;
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end if;
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end if;
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vready := '1';
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v.state := "000";
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end case;
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divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
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if (divi.flush = '1') then v.state := "000"; end if;
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if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
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v.state := RRES.state; v.cnt := RRES.cnt;
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end if;
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rin <= v;
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divo.ready <= vready; divo.nready <= vnready;
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divo.result(31 downto 0) <= r.x(63 downto 32);
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addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
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end process;
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divadd : process(addin1, addin2, addsub)
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variable b : std_logic_vector(32 downto 0);
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begin
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if addsub = '1' then b := not addin2; else b := addin2; end if;
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addout <= addin1 + b + addsub;
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end process;
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syncrregs : if not ASYNC_RESET generate
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reg : process(clk)
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begin
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if rising_edge(clk) then
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if (holdn = '1') then r <= rin; end if;
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if (rst = '0') then
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if RESET_ALL then
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r <= RRES;
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else
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r.state <= RRES.state; r.cnt <= RRES.cnt;
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end if;
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end if;
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end if;
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end process;
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end generate syncrregs;
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asyncrregs : if ASYNC_RESET generate
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reg : process(clk, arst)
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begin
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if (arst = '0') then
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r <= RRES;
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elsif rising_edge(clk) then
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if (holdn = '1') then r <= rin; end if;
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end if;
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end process;
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end generate asyncrregs;
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end;
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