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68 lines
2.9 KiB
Text
68 lines
2.9 KiB
Text
SDRAM controller enable
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CONFIG_DDR2SP
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Say Y here to enabled a 16-bit DDR266 SDRAM controller.
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Power-on init
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CONFIG_DDR2SP_INIT
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Say Y here to enable the automatic DDR initialization sequence.
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If disabled, the sequencemust be performed in software before
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the DDR can be used. If unsure, say Y.
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Synchronization
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CONFIG_DDR2SP_NOSYNC
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Say Y here if the DDR clock and system clock are aligned so
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that the DDR clock always has a rising edge at the same instant
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as the system clock has a risning edge. If this value is set to
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Y, synchronization registers in the controller will not be
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instantiated. This leads to lower latency in the controller but
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leads to the requirement above on the input clocks. This option
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is not valid in all template designs. If unsure, say no.
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Memory frequency
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CONFIG_DDR2SP_FREQ
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Enter the frequency of the DDR clock (in MHz). The value is
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typically between 130 - 200, depending on system configuration.
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Some template designs (such as the leon3-avnet-eval-lx25)
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calculate this value automatically and this value is not used.
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Refresh to Activate
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CONFIG_DDR2SP_TRFC
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Enter the Refresh to Activate timing (tRFC) in ns. The value is
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typically between 75 - 130, depending on memory chip implementation.
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DDR2 Data width
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CONFIG_DDR2SP_DATAWIDTH
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Select the width of the DDR2 data bus. 64-bit or 32-bit or
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16-bit can be selected. Only used in some template designs.
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Column bits
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CONFIG_DDR2SP_COL
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Select the number of colomn address bits of the DDR memory.
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Typical values are 8 - 11. Only needed when automatic DDR
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initialisation is choosen. The column size can always be
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programmed by software as well.
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Chip select size
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CONFIG_DDR2SP_MBYTE
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Select the memory size (Mbytes) that each chip select should decode.
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Only needed when automatic DDR initialisation is choosen. The chip
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select size can always be programmed by software as well.
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Read data delay
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CONFIG_DDR2SP_DELAY0 CONFIG_DDR2SP_DELAY1 CONFIG_DDR2SP_DELAY2 CONFIG_DDR2SP_DELAY3 CONFIG_DDR2SP_DELAY4 CONFIG_DDR2SP_DELAY5 CONFIG_DDR2SP_DELAY6 CONFIG_DDR2SP_DELAY7 CONFIG_DDR2SP_CBDELAY0 CONFIG_DDR2SP_CBDELAY1 CONFIG_DDR2SP_CBDELAY2 CONFIG_DDR2SP_CBDELAY3
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On Xilinx targets (virtex4 and virtex5), input delays are added to
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all data bits to align read data to the internal DDR clock signal.
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The delay can be set to a value of 0 to 63 tap-delays. Each tap-
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delay equals to ~78ps delay, with an reference clock at 200 MHz.
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This delay value is only a reset valus, it can be changed dynamically
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via a configuration register.
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Fault-Tolenant version
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CONFIG_DDR2SP_FTEN
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Say Y here to enable the fault-tolerant version of the DDR2 controller.
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In this version, the data bus is enlarged by 25% or 50% and the added
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bits are used to store checkbits. The checkbits are generated and
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checked using a Reed-Solomon codec.
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This option is only available in the FT version of GRLIB and supported
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only in some template designs.
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