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213 lines
9.2 KiB
VHDL
213 lines
9.2 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ddr2spa
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-- File: ddr2spa.vhd
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-- Author: Nils-Johan Wessman - Gaisler Research
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-- Description: 16-, 32- or 64-bit DDR2 memory controller module.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use grlib.devices.all;
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use gaisler.ddrpkg.all;
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library techmap;
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use techmap.gencomp.all;
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entity ddr2spa is
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generic (
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fabtech : integer := virtex4;
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memtech : integer := 0;
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rskew : integer := 0;
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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MHz : integer := 100;
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TRFC : integer := 130;
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clkmul : integer := 2;
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clkdiv : integer := 2;
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col : integer := 9;
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Mbyte : integer := 16;
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rstdel : integer := 200;
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pwron : integer := 0;
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oepol : integer := 0;
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ddrbits : integer := 16;
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ahbfreq : integer := 50;
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readdly : integer := 1; -- 1 added read latency cycle
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ddelayb0 : integer := 0; -- Data delay value (0 - 63)
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ddelayb1 : integer := 0; -- Data delay value (0 - 63)
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ddelayb2 : integer := 0; -- Data delay value (0 - 63)
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ddelayb3 : integer := 0; -- Data delay value (0 - 63)
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ddelayb4 : integer := 0; -- Data delay value (0 - 63)
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ddelayb5 : integer := 0; -- Data delay value (0 - 63)
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ddelayb6 : integer := 0; -- Data delay value (0 - 63)
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ddelayb7 : integer := 0; -- Data delay value (0 - 63)
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cbdelayb0 : integer := 0; -- Data delay value (0 - 63)
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cbdelayb1 : integer := 0; -- Data delay value (0 - 63)
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cbdelayb2 : integer := 0; -- Data delay value (0 - 63)
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cbdelayb3 : integer := 0; -- Data delay value (0 - 63)
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numidelctrl : integer := 4;
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norefclk : integer := 0;
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odten : integer := 0;
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octen : integer := 0;
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dqsgating : integer := 0;
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nosync : integer := 0; -- Disable sync registers at CD crossings
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eightbanks : integer range 0 to 1 := 0;
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dqsse : integer range 0 to 1 := 0; -- single ended DQS
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burstlen : integer range 4 to 128 := 8;
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ahbbits : integer := ahbdw;
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ft : integer range 0 to 1 := 0;
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ftbits : integer := 0;
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bigmem : integer range 0 to 1 := 0;
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raspipe : integer range 0 to 1 := 0;
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nclk : integer range 1 to 3 := 3;
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scantest : integer := 0;
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ncs : integer := 2;
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cke_rst : integer := 0;
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pipe_ctrl : integer := 0
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);
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port (
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rst_ddr : in std_ulogic;
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rst_ahb : in std_ulogic;
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clk_ddr : in std_ulogic;
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clk_ahb : in std_ulogic;
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clkref200 : in std_logic;
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lock : out std_ulogic; -- DCM locked
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clkddro : out std_ulogic; -- DDR clock
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clkddri : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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ddr_clk : out std_logic_vector(nclk-1 downto 0);
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ddr_clkb : out std_logic_vector(nclk-1 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
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ddr_dqsn : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
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ddr_ad : out std_logic_vector(13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector(1+eightbanks downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector((ddrbits+ftbits)-1 downto 0); -- ddr data
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ddr_odt : out std_logic_vector(1 downto 0);
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ce : out std_logic; -- Corrected error (for FT)
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oct_rdn : in std_logic := '0';
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oct_rup : in std_logic := '0'
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);
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end;
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architecture rtl of ddr2spa is
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constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
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signal sdi : ddrctrl_in_type;
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signal sdo : ddrctrl_out_type;
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--signal clkread : std_ulogic;
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-- Reset scheme:
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-- 1. rst_ddr inport is a raw async reset brought in from the outside - goes to PHY/PLL:s
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-- 2. lock signal from PHY/PLLs goes out through lock outport to external
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-- ahb rstgen and internal ddr reset gen
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-- 3. AMBA synchronous reset signal rst_ahb comes back in
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-- DDR Clock scheme:
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-- 1. clk_ddr (and clkref200) goes into PHY
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-- 2. clkddro comes out from PHY and goes out through clkddro port
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-- 3. clkddri comes back in and is used to clock DDR-side logic
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signal ilock: std_ulogic;
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signal ddr_rst: std_logic;
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signal ddr_rst_gen: std_logic_vector(3 downto 0);
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constant ddr_syncrst: integer := 0;
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begin
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lock <= ilock;
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ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1)); -- Reset signal in DDR clock domain
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ddrrstproc: process(clkddri, ilock)
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begin
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if rising_edge(clkddri) then
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ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
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if ddr_syncrst /= 0 and rst_ahb='0' then
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ddr_rst_gen <= "0000";
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end if;
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end if;
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if ddr_syncrst=0 and ilock='0' then
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ddr_rst_gen <= "0000";
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end if;
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end process;
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nftphy: if true generate
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ddr_phy0 : ddr2phy_wrap_cbd
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generic map (
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tech => fabtech, MHz => MHz,
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dbits => ddrbits, rstdelay => 0, clk_mul => clkmul,
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clk_div => clkdiv,
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ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
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ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
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ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, cbdelayb0=> cbdelayb0,
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cbdelayb1=> cbdelayb1, cbdelayb2=> cbdelayb2,cbdelayb3=> cbdelayb3,
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numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
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eightbanks => eightbanks, dqsse => dqsse,
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chkbits => ftbits*ft, padbits => ftbits*(1-ft),
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ctrl2en => 0, resync => 0, custombits => 8,
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nclk => nclk, scantest => scantest, ncs => ncs )
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port map (
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rst_ddr, clk_ddr, clkref200, clkddro, clkddri, clkddri, ilock,
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ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
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ddr_cke(ncs-1 downto 0), ddr_csb(ncs-1 downto 0), ddr_web, ddr_rasb, ddr_casb,
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ddr_dm, ddr_dqs, ddr_dqsn,
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ddr_ad, ddr_ba, ddr_dq, ddr_odt(ncs-1 downto 0),
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open, open, open, open, open,
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sdi, sdo, clkddri, "00000000", open,
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ahbsi.testen, ahbsi.scanen, ahbsi.testrst, ahbsi.testoen,
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oct_rdn, oct_rup);
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ncs1: if ncs = 1 generate
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ddr_cke(1) <= '0';
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ddr_csb(1) <= '0';
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ddr_odt(1) <= '0';
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end generate;
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end generate;
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ddrc : ddr2spax generic map (memtech => memtech, phytech => fabtech, hindex => hindex,
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haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask, ddrbits => ddrbits,
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pwron => pwron, MHz => DDR_FREQ, TRFC => TRFC, col => col, Mbyte => Mbyte,
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readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
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nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen, ahbbits => ahbbits,
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ft => ft, ddr_syncrst => ddr_syncrst, bigmem => bigmem, raspipe => raspipe, hwidthen => 0, rstdel => rstdel,
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cke_rst => cke_rst, pipe_ctrl => pipe_ctrl)
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port map (ddr_rst, rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo, '0');
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ce <= sdo.ce;
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end;
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