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40 lines
1.6 KiB
Text
40 lines
1.6 KiB
Text
SDRAM controller enable
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CONFIG_DDRSP
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Say Y here to enabled a 16-bit DDR266 SDRAM controller.
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Power-on init
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CONFIG_DDRSP_INIT
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Say Y here to enable the automatic DDR initialization sequence.
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If disabled, the sequencemust be performed in software before
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the DDR can be used. If unsure, say Y.
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Memory frequency
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CONFIG_DDRSP_FREQ
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Enter the frequency of the DDR clock (in MHz). The value is
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typically between 80 - 133, depending on system configuration.
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Some template design (such as the leon3-avnet-eval-lx25)
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calculate this value automatically and this value is not used.
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Column bits
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CONFIG_DDRSP_COL
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Select the number of colomn address bits of the DDR memory.
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Typical values are 8 - 11. Only needed when automatic DDR
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initialisation is choosen. The column size can always be
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programmed by software as well.
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Chip select size
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CONFIG_DDRSP_MBYTE
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Select the memory size (Mbytes) that each chip select should decode.
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Only needed when automatic DDR initialisation is choosen. The chip
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select size can always be programmed by software as well.
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Read clock phase shift
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CONFIG_DDRSP_RSKEW
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On Xilinx targets, the read clock is de-skewed and phase-shifted
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using a DCM connected to the feed-back clock input. On some boards,
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the de-skewing does not work perfectly, and some extra phase shifting
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must be added manually. The entered value is set to the PHASE_SHIFT
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generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
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needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
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For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of
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the PLL in ps (e.g 2500 for 90' shift in 100MHz)
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