mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-23 13:07:08 -04:00
92 lines
3.9 KiB
Text
92 lines
3.9 KiB
Text
mainmenu_option next_comment
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comment '8/32-bit PROM/SRAM controller with EDAC'
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bool 'Enable 32-bit PROM/SRAM controller ' CONFIG_SRCTRLFT
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if [ "$CONFIG_SRCTRLFT" = "y" ]; then
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bool 'Enable APB interface' CONFIG_SRCTRLFT_APBEN
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if [ "$CONFIG_SRCTRLFT_APBEN" != "y" ]; then
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int 'PROM waitstates' CONFIG_SRCTRLFT_PROMWS 3
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int 'RAM waitstates' CONFIG_SRCTRLFT_RAMWS 0
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int 'IO waitstates' CONFIG_SRCTRLFT_IOWS 0
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fi
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bool 'Use read-modify-write for sub-word writes ' CONFIG_SRCTRLFT_RMW
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bool '8-bit PROM interface ' CONFIG_SRCTRLFT_8BIT
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bool 'Enable EDAC ' CONFIG_SRCTRLFT_EDAC
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choice 'SRAM banks' \
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"1 CONFIG_SRCTRLFT_SRBANKS1 \
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2 CONFIG_SRCTRLFT_SRBANKS2 \
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3 CONFIG_SRCTRLFT_SRBANKS3 \
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4 CONFIG_SRCTRLFT_SRBANKS4 \
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5 CONFIG_SRCTRLFT_SRBANKS5 \
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6 CONFIG_SRCTRLFT_SRBANKS6 \
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7 CONFIG_SRCTRLFT_SRBANKS7 \
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8 CONFIG_SRCTRLFT_SRBANKS8" 1
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choice 'SRAM fixed bank size, or programmable' \
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" programmable CONFIG_SRCTRLFT_BANKSZ0 \
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16_kByte CONFIG_SRCTRLFT_BANKSZ1 \
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32_kByte CONFIG_SRCTRLFT_BANKSZ2 \
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64_kByte CONFIG_SRCTRLFT_BANKSZ3 \
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128_kByte CONFIG_SRCTRLFT_BANKSZ4 \
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256_kByte CONFIG_SRCTRLFT_BANKSZ5 \
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512_kByte CONFIG_SRCTRLFT_BANKSZ6 \
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1_MByte CONFIG_SRCTRLFT_BANKSZ7 \
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2_MByte CONFIG_SRCTRLFT_BANKSZ8 \
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4_MByte CONFIG_SRCTRLFT_BANKSZ9 \
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8_MByte CONFIG_SRCTRLFT_BANKSZ10 \
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16_MByte CONFIG_SRCTRLFT_BANKSZ11 \
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32_MByte CONFIG_SRCTRLFT_BANKSZ12 \
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64_MByte CONFIG_SRCTRLFT_BANKSZ13 \
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128_MByte CONFIG_SRCTRLFT_BANKSZ14 \
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256_MByte CONFIG_SRCTRLFT_BANKSZ15" 0
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choice 'PROM banks' \
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"1 CONFIG_SRCTRLFT_ROMBANKS1 \
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2 CONFIG_SRCTRLFT_ROMBANKS2 \
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3 CONFIG_SRCTRLFT_ROMBANKS3 \
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4 CONFIG_SRCTRLFT_ROMBANKS4 \
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5 CONFIG_SRCTRLFT_ROMBANKS5 \
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6 CONFIG_SRCTRLFT_ROMBANKS6 \
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7 CONFIG_SRCTRLFT_ROMBANKS7 \
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8 CONFIG_SRCTRLFT_ROMBANKS8" 1
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choice 'PROM fixed bank size, or programmable' \
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" programmable CONFIG_SRCTRLFT_ROMBANKSZ0 \
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16_kByte CONFIG_SRCTRLFT_ROMBANKSZ1 \
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32_kByte CONFIG_SRCTRLFT_ROMBANKSZ2 \
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64_kByte CONFIG_SRCTRLFT_ROMBANKSZ3 \
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128_kByte CONFIG_SRCTRLFT_ROMBANKSZ4 \
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256_kByte CONFIG_SRCTRLFT_ROMBANKSZ5 \
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512_kByte CONFIG_SRCTRLFT_ROMBANKSZ6 \
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1_MByte CONFIG_SRCTRLFT_ROMBANKSZ7 \
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2_MByte CONFIG_SRCTRLFT_ROMBANKSZ8 \
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4_MByte CONFIG_SRCTRLFT_ROMBANKSZ9 \
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8_MByte CONFIG_SRCTRLFT_ROMBANKSZ10 \
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16_MByte CONFIG_SRCTRLFT_ROMBANKSZ11 \
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32_MByte CONFIG_SRCTRLFT_ROMBANKSZ12 \
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64_MByte CONFIG_SRCTRLFT_ROMBANKSZ13 \
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128_MByte CONFIG_SRCTRLFT_ROMBANKSZ14 \
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256_MByte CONFIG_SRCTRLFT_ROMBANKSZ15" 0
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if [ "$CONFIG_SRCTRLFT_ROMBANKSZ0" = "1" ]; then
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choice 'PROM default bank size, when programmable' \
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" 8_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF0 \
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16_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF1 \
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32_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF2 \
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64_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF3 \
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128_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF4 \
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256_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF5 \
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512_kByte CONFIG_SRCTRLFT_ROMBANKSZDEF6 \
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1_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF7 \
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2_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF8 \
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4_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF9 \
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8_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF10 \
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16_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF11 \
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32_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF12 \
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64_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF13 \
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128_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF14 \
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256_MByte CONFIG_SRCTRLFT_ROMBANKSZDEF15" 0
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fi
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fi
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bool 'Use VHDL/EDIF netlist ' CONFIG_SRCTRLFT_NETLIST
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endmenu
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