mirror of
https://github.com/lcbcFoo/ReonV.git
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583 lines
19 KiB
VHDL
583 lines
19 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: pci
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-- File: pci.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Package with component and type declarations for PCI cores
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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package pci is
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type pci_in_type is record
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rst : std_ulogic;
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gnt : std_ulogic;
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idsel : std_ulogic;
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ad : std_logic_vector(31 downto 0);
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cbe : std_logic_vector(3 downto 0);
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frame : std_ulogic;
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irdy : std_ulogic;
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trdy : std_ulogic;
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devsel : std_ulogic;
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stop : std_ulogic;
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lock : std_ulogic;
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perr : std_ulogic;
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serr : std_ulogic;
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par : std_ulogic;
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host : std_ulogic;
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pci66 : std_ulogic;
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pme_status : std_ulogic;
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int : std_logic_vector(3 downto 0); -- D downto A
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end record;
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constant pci_in_none : pci_in_type := (
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rst => '0',
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gnt => '0',
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idsel => '0',
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ad => (others => '0'),
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cbe => (others => '0'),
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frame => '0',
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irdy => '0',
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trdy => '0',
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devsel => '0',
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stop => '0',
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lock => '0',
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perr => '0',
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serr => '0',
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par => '0',
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host => '0',
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pci66 => '0',
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pme_status => '0',
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int => (others => '0'));
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type pci_out_type is record
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aden : std_ulogic;
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vaden : std_logic_vector(31 downto 0);
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cbeen : std_logic_vector(3 downto 0);
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frameen : std_ulogic;
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irdyen : std_ulogic;
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trdyen : std_ulogic;
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devselen : std_ulogic;
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stopen : std_ulogic;
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ctrlen : std_ulogic;
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perren : std_ulogic;
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paren : std_ulogic;
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reqen : std_ulogic;
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locken : std_ulogic;
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serren : std_ulogic;
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inten : std_logic;
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vinten : std_logic_vector(3 downto 0);
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req : std_ulogic;
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ad : std_logic_vector(31 downto 0);
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cbe : std_logic_vector(3 downto 0);
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frame : std_ulogic;
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irdy : std_ulogic;
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trdy : std_ulogic;
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devsel : std_ulogic;
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stop : std_ulogic;
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perr : std_ulogic;
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serr : std_ulogic;
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par : std_ulogic;
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lock : std_ulogic;
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power_state : std_logic_vector(1 downto 0);
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pme_enable : std_ulogic;
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pme_clear : std_ulogic;
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int : std_logic;
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rst : std_ulogic;
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end record;
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constant pci_out_none : pci_out_type := (
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aden => '1', vaden => (others => '1'), cbeen => (others => '1'),
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frameen => '1', irdyen => '1', trdyen => '1', devselen => '1',
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stopen => '1', ctrlen => '1', perren => '1', paren => '1', reqen => '1',
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locken => '1', serren => '1', inten => '1', vinten => (others => '1'), req => '1', ad => (others => '0'),
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cbe => (others => '1'), frame => '1', irdy => '1', trdy => '1', devsel => '1',
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stop => '1', perr => '1', serr => '1', par => '1', lock => '1',
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power_state => (others => '1'), pme_enable => '1',pme_clear => '1',
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int => '1', rst => '1');
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component pci_target
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generic (
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hindex : integer := 0;
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abits : integer := 21;
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
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oepol : integer := 0
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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pciclk : in std_ulogic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type
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);
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end component;
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component pci_mt
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generic (
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hmstndx : integer := 0;
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abits : integer := 21;
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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master : integer := 1; -- Enable PCI Master
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hslvndx : integer := 0;
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haddr : integer := 16#F00#;
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hmask : integer := 16#F00#;
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ioaddr : integer := 16#000#;
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nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
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oepol : integer := 0
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);
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port(
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rst : in std_logic;
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clk : in std_logic;
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pciclk : in std_logic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end component;
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component dmactrl
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generic (
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hindex : integer := 0;
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slvindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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blength : integer := 4);
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port (
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rst : in std_logic;
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clk : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi0 : in ahb_slv_in_type;
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ahbso0 : out ahb_slv_out_type;
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ahbsi1 : out ahb_slv_in_type;
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ahbso1 : in ahb_slv_out_type);
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end component;
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component pci_mtf
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generic (
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memtech : integer := DEFMEMTECH;
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hmstndx : integer := 0;
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dmamst : integer := NAHBMST;
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readpref : integer := 0;
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abits : integer := 21;
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dmaabits : integer := 26;
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fifodepth : integer := 3; -- FIFO depth
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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master : integer := 1; -- Enable PCI Master
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hslvndx : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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haddr : integer := 16#F00#;
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hmask : integer := 16#F00#;
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ioaddr : integer := 16#000#;
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irq : integer := 0;
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irqmask : integer := 0;
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nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
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oepol : integer := 0;
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endian : integer := 0;
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class_code: integer := 16#0B4000#;
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rev : integer := 0;
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scanen : integer := 0;
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syncrst : integer := 0;
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hostrst : integer := 0);
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port(
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rst : in std_logic;
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clk : in std_logic;
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pciclk : in std_logic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end component;
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component pcitrace
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generic (
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depth : integer range 6 to 12 := 8;
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iregs : integer := 1;
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memtech : integer := DEFMEMTECH;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#f00#
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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pciclk : in std_ulogic;
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pcii : in pci_in_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type
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);
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end component;
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component pcipads
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generic (
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padtech : integer := 0;
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noreset : integer := 0;
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oepol : integer := 0;
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host : integer := 1;
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int : integer := 0;
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no66 : integer := 0;
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onchipreqgnt : integer := 0;
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drivereset : integer := 0;
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constidsel : integer := 0;
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level : integer := pci33;
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voltage : integer := x33v;
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singleint : integer := 0;
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nolock : integer := 0
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);
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port (
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pci_rst : inout std_logic;
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pci_gnt : in std_ulogic;
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pci_idsel : in std_ulogic;
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pci_lock : inout std_ulogic;
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_cbe : inout std_logic_vector(3 downto 0);
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pci_frame : inout std_logic;
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pci_irdy : inout std_logic;
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pci_trdy : inout std_logic;
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pci_devsel : inout std_logic;
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pci_stop : inout std_logic;
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pci_perr : inout std_logic;
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pci_par : inout std_logic;
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pci_req : inout std_logic; -- tristate pad but never read
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pci_serr : inout std_logic; -- open drain output
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pci_host : in std_ulogic;
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pci_66 : in std_ulogic;
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pcii : out pci_in_type;
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pcio : in pci_out_type;
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pci_int : inout std_logic_vector(3*(1-singleint) downto 0)
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);
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end component;
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component pcidma
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generic (
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memtech : integer := DEFMEMTECH;
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dmstndx : integer := 0;
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dapbndx : integer := 0;
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dapbaddr : integer := 0;
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dapbmask : integer := 16#fff#;
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dapbirq : integer := 0;
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blength : integer := 16;
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mstndx : integer := 0;
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abits : integer := 21;
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dmaabits : integer := 26;
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fifodepth : integer := 3; -- FIFO depth
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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slvndx : integer := 0;
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apbndx : integer := 0;
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apbaddr : integer := 0;
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apbmask : integer := 16#fff#;
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haddr : integer := 16#F00#;
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hmask : integer := 16#F00#;
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ioaddr : integer := 16#000#;
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nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
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oepol : integer := 0;
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endian : integer := 0; -- 0 little, 1 big
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class_code: integer := 16#0B4000#;
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rev : integer := 0;
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irq : integer := 0;
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irqmask : integer := 0;
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scanen : integer := 0;
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hostrst : integer := 0;
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syncrst : integer := 0);
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port(
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rst : in std_logic;
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clk : in std_logic;
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pciclk : in std_logic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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dapbo : out apb_slv_out_type;
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dahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end component;
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type pci_ahb_dma_in_type is record
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address : std_logic_vector(31 downto 0);
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wdata : std_logic_vector(31 downto 0);
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start : std_ulogic;
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burst : std_ulogic;
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write : std_ulogic;
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busy : std_ulogic;
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irq : std_ulogic;
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size : std_logic_vector(1 downto 0);
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end record;
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type pci_ahb_dma_out_type is record
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start : std_ulogic;
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active : std_ulogic;
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ready : std_ulogic;
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retry : std_ulogic;
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mexc : std_ulogic;
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haddr : std_logic_vector(9 downto 0);
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rdata : std_logic_vector(31 downto 0);
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end record;
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component pciahbmst
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generic (
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hindex : integer := 0;
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hirq : integer := 0;
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venid : integer := VENDOR_GAISLER;
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devid : integer := 0;
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version : integer := 0;
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chprot : integer := 3;
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incaddr : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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dmai : in pci_ahb_dma_in_type;
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dmao : out pci_ahb_dma_out_type;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type
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);
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end component;
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component pcif
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generic (
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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class : integer := 0;
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revision_id : integer := 0;
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aaddr_width : integer := 28;
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maddr_width : integer := 28;
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pcibars : integer := 1;
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ahbmasters : integer := 8;
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fifo_depth : integer := 3;
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ft : integer := 0;
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memtech : integer := 0;
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hmstndx : integer := 0;
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hslvndx : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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haddr : integer := 16#F00#;
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hmask : integer := 16#F00#);
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port(
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rst : in std_logic;
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pciclk : in std_logic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type);
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--debug : out std_logic_vector(233 downto 0));
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end component;
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component pcif_async
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generic (
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device_id : integer := 0; -- PCI device ID
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vendor_id : integer := 0; -- PCI vendor ID
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class : integer := 0;
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revision_id : integer := 0;
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bar1 : integer := 20;
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bar2 : integer := 24;
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bar3 : integer := 0;
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bar4 : integer := 0;
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ahbmasters : integer := 28;
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fifo_depth : integer := 1;
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ft : integer := 0;
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nsync : integer := 2;
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irqctrl : integer := 0;
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host : integer := 0;
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memtech : integer := 0;
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hmstndx : integer := 0;
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hslvndx : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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haddr : integer := 16#F00#;
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hmask : integer := 16#F00#;
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ioaddr : integer := 16#000#;
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pirq : integer := 0;
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netlist : integer := 0;
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debugen : integer := 0;
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hostrst : integer := 0
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);
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port(
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rst : in std_logic;
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clk : in std_logic;
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pcirst : in std_logic;
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pciclk : in std_logic;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type--;
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--debug : out std_logic_vector(255 downto 0)
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);
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end component;
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|
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component grpci2
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generic (
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memtech : integer := DEFMEMTECH;
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tbmemtech : integer := DEFMEMTECH;
|
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oepol : integer := 0;
|
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hmindex : integer := 0;
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hdmindex : integer := 0;
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hsindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 0;
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ioaddr : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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irq : integer := 0;
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irqmode : integer range 0 to 3 := 0;
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master : integer range 0 to 1 := 1;
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target : integer range 0 to 1 := 1;
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|
dma : integer range 0 to 1 := 1;
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|
tracebuffer : integer range 0 to 16384 := 0;
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|
confspace : integer range 0 to 1 := 1;
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vendorid : integer := 16#0000#;
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deviceid : integer := 16#0000#;
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classcode : integer := 16#000000#;
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revisionid : integer := 16#00#;
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cap_pointer : integer := 16#40#;
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|
ext_cap_pointer : integer := 16#00#;
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|
iobase : integer := 16#FFF#;
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|
extcfg : integer := 16#0000000#;
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|
bar0 : integer range 0 to 31 := 28;
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|
bar1 : integer range 0 to 31 := 0;
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|
bar2 : integer range 0 to 31 := 0;
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|
bar3 : integer range 0 to 31 := 0;
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|
bar4 : integer range 0 to 31 := 0;
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|
bar5 : integer range 0 to 31 := 0;
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|
bar0_map : integer := 16#000000#;
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|
bar1_map : integer := 16#000000#;
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|
bar2_map : integer := 16#000000#;
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|
bar3_map : integer := 16#000000#;
|
|
bar4_map : integer := 16#000000#;
|
|
bar5_map : integer := 16#000000#;
|
|
bartype : integer range 0 to 65535 := 16#0000#;
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|
barminsize : integer range 5 to 31 := 12;
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|
fifo_depth : integer range 3 to 7 := 3;
|
|
fifo_count : integer range 2 to 4 := 2;
|
|
conv_endian : integer range 0 to 1 := 0; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
|
|
deviceirq : integer range 0 to 1 := 1;
|
|
deviceirqmask : integer range 0 to 15 := 16#0#;
|
|
hostirq : integer range 0 to 1 := 1;
|
|
hostirqmask : integer range 0 to 15 := 16#0#;
|
|
nsync : integer range 0 to 2 := 2;
|
|
hostrst : integer range 0 to 2 := 0;-- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
|
|
bypass : integer range 0 to 1 := 1;
|
|
ft : integer range 0 to 1 := 0;
|
|
scantest : integer range 0 to 1 := 0;
|
|
debug : integer range 0 to 1 := 0;
|
|
tbapben : integer range 0 to 1 := 0;
|
|
tbpindex : integer := 0;
|
|
tbpaddr : integer := 0;
|
|
tbpmask : integer := 16#F00#;
|
|
netlist : integer range 0 to 1 := 0;
|
|
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
|
|
multiint : integer range 0 to 1 := 0;
|
|
masters : integer := 16#FFFF#;
|
|
mf1_deviceid : integer := 16#0000#;
|
|
mf1_classcode : integer := 16#000000#;
|
|
mf1_revisionid : integer := 16#00#;
|
|
mf1_bar0 : integer range 0 to 31 := 0;
|
|
mf1_bar1 : integer range 0 to 31 := 0;
|
|
mf1_bar2 : integer range 0 to 31 := 0;
|
|
mf1_bar3 : integer range 0 to 31 := 0;
|
|
mf1_bar4 : integer range 0 to 31 := 0;
|
|
mf1_bar5 : integer range 0 to 31 := 0;
|
|
mf1_bartype : integer range 0 to 65535 := 16#0000#;
|
|
mf1_bar0_map : integer := 16#000000#;
|
|
mf1_bar1_map : integer := 16#000000#;
|
|
mf1_bar2_map : integer := 16#000000#;
|
|
mf1_bar3_map : integer := 16#000000#;
|
|
mf1_bar4_map : integer := 16#000000#;
|
|
mf1_bar5_map : integer := 16#000000#;
|
|
mf1_cap_pointer : integer := 16#40#;
|
|
mf1_ext_cap_pointer : integer := 16#00#;
|
|
mf1_extcfg : integer := 16#0000000#;
|
|
mf1_masters : integer := 16#0000#;
|
|
iotest : integer := 0);
|
|
port(
|
|
rst : in std_logic;
|
|
clk : in std_logic;
|
|
pciclk : in std_logic;
|
|
dirq : in std_logic_vector(3 downto 0);
|
|
pcii : in pci_in_type;
|
|
pcio : out pci_out_type;
|
|
apbi : in apb_slv_in_type;
|
|
apbo : out apb_slv_out_type;
|
|
ahbsi : in ahb_slv_in_type;
|
|
ahbso : out ahb_slv_out_type;
|
|
ahbmi : in ahb_mst_in_type;
|
|
ahbmo : out ahb_mst_out_type;
|
|
ahbdmi : in ahb_mst_in_type;
|
|
ahbdmo : out ahb_mst_out_type;
|
|
ptarst : out std_logic;
|
|
tbapbi : in apb_slv_in_type := apb_slv_in_none;
|
|
tbapbo : out apb_slv_out_type;
|
|
debugo : out std_logic_vector(debug*255 downto 0)
|
|
);
|
|
end component;
|
|
|
|
constant PCI_VENDOR_ESA : integer := 16#16E3#;
|
|
constant PCI_VENDOR_GAISLER : integer := 16#1AC8#;
|
|
constant PCI_VENDOR_AEROFLEX : integer := 16#1AD0#;
|
|
|
|
end;
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|
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