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277 lines
11 KiB
VHDL
277 lines
11 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: pcipads
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-- File: pcipads.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: PCI pads module
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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use work.pci.all;
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library grlib;
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use grlib.stdlib.all;
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entity pcipads is
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generic (
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padtech : integer := 0;
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noreset : integer := 0;
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oepol : integer := 0;
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host : integer := 1;
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int : integer := 0;
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no66 : integer := 0;
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onchipreqgnt : integer := 0; -- Internal req and gnt signals
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drivereset : integer := 0; -- Drive PCI rst with outpad
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constidsel : integer := 0; -- pci_idsel is tied to local constant
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level : integer := pci33; -- input/output level
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voltage : integer := x33v; -- input/output voltage
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nolock : integer := 0;
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singleint : integer := 0
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);
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port (
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pci_rst : inout std_logic;
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pci_gnt : in std_ulogic;
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pci_idsel : in std_ulogic;
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pci_lock : inout std_ulogic;
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_cbe : inout std_logic_vector(3 downto 0);
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pci_frame : inout std_ulogic;
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pci_irdy : inout std_ulogic;
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pci_trdy : inout std_ulogic;
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pci_devsel : inout std_ulogic;
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pci_stop : inout std_ulogic;
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pci_perr : inout std_ulogic;
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pci_par : inout std_ulogic;
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pci_req : inout std_ulogic; -- tristate pad but never read
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pci_serr : inout std_ulogic; -- open drain output
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pci_host : in std_ulogic;
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pci_66 : in std_ulogic;
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pcii : out pci_in_type;
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pcio : in pci_out_type;
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pci_int : inout std_logic_vector(3*(1-singleint) downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
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--pci_int : inout std_logic_vector(3 downto 0) :=
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-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
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);
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end;
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architecture rtl of pcipads is
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signal vcc : std_ulogic;
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begin
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vcc <= '1';
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-- Reset
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rstpad : if noreset = 0 generate
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nodrive: if drivereset = 0 generate
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pci_rst_pad : iodpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => 0)
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port map (pci_rst, pcio.rst, pcii.rst);
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end generate nodrive;
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drive: if drivereset /= 0 generate
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pci_rst_pad : outpad generic map (tech => padtech, level => level,
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voltage => voltage)
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port map (pci_rst, pcio.rst);
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pcii.rst <= pcio.rst;
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end generate drive;
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end generate;
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norstpad : if noreset = 1 generate
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pcii.rst <= pci_rst;
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end generate;
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localgnt: if onchipreqgnt = 1 generate
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pcii.gnt <= pci_gnt;
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pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
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end generate localgnt;
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extgnt: if onchipreqgnt = 0 generate
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pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
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pad_pci_req : toutpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_req, pcio.req, pcio.reqen);
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end generate extgnt;
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idsel_pad: if constidsel = 0 generate
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pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
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end generate idsel_pad;
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idsel_local: if constidsel /= 0 generate
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pcii.idsel <= pci_idsel;
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end generate idsel_local;
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onlyhost : if host = 2 generate
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pcii.host <= '0'; -- Always host
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end generate;
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dohost : if host = 1 generate
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pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
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end generate;
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nohost : if host = 0 generate
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pcii.host <= '1'; -- disable pci host functionality
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end generate;
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do66 : if no66 = 0 generate
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pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
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end generate;
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dono66 : if no66 = 1 generate
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pcii.pci66 <= '0';
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end generate;
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dolock : if nolock = 0 generate
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pad_pci_lock : iopad
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generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
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end generate;
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donolock : if nolock = 1 generate
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pcii.lock <= pci_lock;
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end generate;
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pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
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voltage => voltage, width => 32,
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oepol => oepol)
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port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
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pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
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pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
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pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
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pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
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pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
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pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
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pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
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pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
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pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
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pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
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pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_par, pcio.par, pcio.paren, pcii.par);
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pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
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port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
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-- PCI interrupt pads
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-- int = 0 and singleint = 0=> no interrupt
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-- int = 0 and singleint = 1=> PCI_INT[A] inout on pci_int(0), other pins not
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-- existing
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-- the cases below are all withsingle int = 0:
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-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
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-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
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-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
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-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
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-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
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-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
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-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
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-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
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-- int = 14 => PCI_INT[A,B,C,D] = in
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-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
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-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
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-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
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-- int = 103 => PCI_INT[A,B,C,D] = out
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-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
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-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
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-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
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-- int = 113 => PCI_INT[A,B,C,D] = inout
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--
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--
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interrupt : if int /= 0 and singleint = 0 generate
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x : for i in 0 to (3*(1-singleint)) generate
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xo : if i = int - 1 and int < 10 generate
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pad_pci_int : odpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_int(i), pcio.inten);
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end generate;
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xonon : if i /= int - 1 and int < 10 and int < 100 generate
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pci_int(i) <= '1';
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end generate;
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xio : if i = (int - 10) and int >= 10 and int < 100 generate
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pad_pci_int : iodpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_int(i), pcio.inten, pcii.int(i));
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end generate;
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xi : if i /= (int - 10) and int >= 10 and int < 100 generate
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pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
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port map (pci_int(i), pcii.int(i));
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end generate;
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x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
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pad_pci_int : odpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_int(i), pcio.vinten(i));
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end generate;
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x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
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pci_int(i) <= '1';
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end generate;
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x2oi : if i <= (int - 110) and int >= 110 generate
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pad_pci_int : iodpad generic map (tech => padtech, level => level,
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voltage => voltage, oepol => oepol)
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port map (pci_int(i), pcio.vinten(i), pcii.int(i));
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end generate;
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x2i : if i > (int - 110) and int >= 110 generate
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pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
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port map (pci_int(i), pcii.int(i));
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end generate;
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end generate;
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end generate;
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nointerrupt : if int = 0 and singleint = 0 generate
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pcii.int <= (others => '0');
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end generate;
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singleinterrupt : if int = 0 and singleint = 1 generate
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pad_pci_int : iodpad
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generic map (
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tech => padtech,
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level => level,
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voltage => voltage,
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oepol => oepol)
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port map (
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pci_int(0),
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pcio.vinten(0),
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pcii.int(0));
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pcii.int(3 downto 1) <= (others => '0');
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end generate;
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pcii.pme_status <= '0';
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end;
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