mirror of
https://github.com/lcbcFoo/ReonV.git
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363 lines
12 KiB
VHDL
363 lines
12 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ahbram
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-- File: ahbram.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Modified: Jan Andersson - Aeroflex Gaisler
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-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
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-- Added Sx-Record read function
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use IEEE.Numeric_Std.all;
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library grlib;
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use grlib.config_types.all;
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use grlib.config.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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use grlib.stdio.all;
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library techmap;
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use techmap.gencomp.all;
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entity ahbram_sim is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#fff#;
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tech : integer := DEFMEMTECH;
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kbytes : integer := 1;
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pipe : integer := 0;
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maccsz : integer := AHBDW;
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fname : string := "ram.dat"
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end;
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architecture rtl of ahbram_sim is
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constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
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constant dw : integer := maccsz;
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constant hconfig : ahb_config_type := (
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0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
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4 => ahb_membar(haddr, '1', '1', hmask),
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others => zero32);
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type reg_type is record
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hwrite : std_ulogic;
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hready : std_ulogic;
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hsel : std_ulogic;
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addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
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size : std_logic_vector(2 downto 0);
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prdata : std_logic_vector((dw-1)*pipe downto 0);
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pwrite : std_ulogic;
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pready : std_ulogic;
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end record;
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constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
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constant RES : reg_type :=
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(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
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size => (others => '0'), prdata => (others => '0'), pwrite => '0',
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pready => '1');
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signal r, c : reg_type;
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signal ramsel : std_logic_vector(dw/8-1 downto 0);
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signal write : std_logic_vector(dw/8-1 downto 0);
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signal ramaddr : std_logic_vector(abits-1 downto 0);
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signal ramdata : std_logic_vector(dw-1 downto 0);
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signal hwdata : std_logic_vector(dw-1 downto 0);
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type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range);
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signal ram : ram_type;
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signal read_address : std_logic_vector(ramaddr'range);
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begin
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comb : process (ahbsi, r, rst, ramdata)
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variable bs : std_logic_vector(dw/8-1 downto 0);
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variable v : reg_type;
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variable haddr : std_logic_vector(abits-1 downto 0);
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variable hrdata : std_logic_vector(dw-1 downto 0);
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variable seldata : std_logic_vector(dw-1 downto 0);
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variable raddr : std_logic_vector(3 downto 2);
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variable adsel : std_logic;
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begin
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v := r; v.hready := '1'; bs := (others => '0');
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v.pready := r.hready;
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if pipe=0 then
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adsel := r.hwrite or not r.hready;
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else
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adsel := r.hwrite or r.pwrite;
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v.hready := r.hready or not r.pwrite;
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end if;
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if adsel = '1' then
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haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
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else
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haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
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bs := (others => '0');
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end if;
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raddr := (others => '0');
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v.pwrite := '0';
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if pipe/=0 and (r.hready='1' or r.pwrite='0') then
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v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
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end if;
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if ahbsi.hready = '1' then
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if pipe=0 then
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v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
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end if;
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v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
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v.size := ahbsi.hsize(2 downto 0);
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v.hwrite := ahbsi.hwrite and v.hsel;
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if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
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v.hready := '0';
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v.pwrite := r.hwrite;
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end if;
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end if;
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if r.hwrite = '1' then
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case r.size is
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when HSIZE_BYTE =>
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bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
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when HSIZE_HWORD =>
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for i in 0 to dw/16-1 loop
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if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
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bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
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end if;
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end loop; -- i
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when HSIZE_WORD =>
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if dw = 32 then bs := (others => '1');
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else
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for i in 0 to dw/32-1 loop
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if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
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bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
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end if;
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end loop; -- i
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end if;
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when HSIZE_DWORD =>
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if dw = 32 then null;
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elsif dw = 64 then bs := (others => '1');
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else
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for i in 0 to dw/64-1 loop
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if i = conv_integer(r.addr(3)) then
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bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
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end if;
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end loop; -- i
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end if;
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when HSIZE_4WORD =>
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if dw < 128 then null;
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elsif dw = 128 then bs := (others => '1');
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else
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for i in 0 to dw/64-1 loop
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if i = conv_integer(r.addr(3)) then
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bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
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end if;
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end loop; -- i
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end if;
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when others => --HSIZE_8WORD
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if dw < 256 then null;
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else bs := (others => '1'); end if;
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end case;
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v.hready := not (v.hsel and not ahbsi.hwrite);
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v.hwrite := v.hwrite and v.hready;
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end if;
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-- Duplicate read data on word basis, unless CORE_ACDM is enabled
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if CORE_ACDM = 0 then
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if dw = 32 then
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seldata := ramdata;
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elsif dw = 64 then
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if r.size = HSIZE_DWORD then seldata := ramdata; else
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if r.addr(2) = '0' then
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seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
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else
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seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
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end if;
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seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
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end if;
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elsif dw = 128 then
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if r.size = HSIZE_4WORD then
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seldata := ramdata;
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elsif r.size = HSIZE_DWORD then
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if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
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else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
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seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
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else
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raddr := r.addr(3 downto 2);
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case raddr is
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when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
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when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
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when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
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when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
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end case;
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seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
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seldata(dw/4-1 downto 0) &
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seldata(dw/4-1 downto 0);
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end if;
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else
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seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
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end if;
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else
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seldata := ramdata;
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end if;
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if pipe = 0 then
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v.prdata := (others => '0');
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hrdata := seldata;
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else
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v.prdata := seldata;
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hrdata := r.prdata;
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end if;
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if (not RESET_ALL) and (rst = '0') then
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v.hwrite := RES.hwrite; v.hready := RES.hready;
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end if;
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write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
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ramaddr <= haddr; c <= v;
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ahbso.hrdata <= ahbdrivedata(hrdata);
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ahbso.hready <= r.hready;
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end process;
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ahbso.hresp <= "00";
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ahbso.hsplit <= (others => '0');
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ahbso.hirq <= (others => '0');
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ahbso.hconfig <= hconfig;
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ahbso.hindex <= hindex;
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-- Select correct write data
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hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
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conv_std_logic_vector(log2(dw/8), 3));
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-- aram : syncrambw generic map (tech, abits, dw, scantest) port map (
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-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
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RamProc: process(clk) is
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variable L1 : line;
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variable FIRST : boolean := true;
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variable ADR : std_logic_vector(19 downto 0);
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variable BUF : std_logic_vector(31 downto 0);
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variable CH : character;
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variable ai : integer := 0;
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variable len : integer := 0;
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file TCF : text open read_mode is fname;
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variable rectype : std_logic_vector(3 downto 0);
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variable recaddr : std_logic_vector(31 downto 0);
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variable reclen : std_logic_vector(7 downto 0);
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variable recdata : std_logic_vector(0 to 16*8-1);
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begin
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if rising_edge(clk) then
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if conv_integer(write) > 0 then
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for i in 0 to dw/8-1 loop
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if (write(i) = '1') then
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ram(to_integer(unsigned(ramaddr)))(i*8+7 downto i*8) <= hwdata(i*8+7 downto i*8);
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end if;
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end loop;
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end if;
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read_address <= ramaddr;
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end if;
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if (rst = '0') and (FIRST = true) then
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ram <= (others => (others => '0'));
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L1:= new string'("");
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while not endfile(TCF) loop
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readline(TCF,L1);
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if (L1'length /= 0) then --'
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while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
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std.textio.read(L1,CH);
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end loop;
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if L1'length > 0 then --'
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read(L1, ch);
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if (ch = 'S') or (ch = 's') then
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hread(L1, rectype);
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hread(L1, reclen);
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len := conv_integer(reclen)-1;
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recaddr := (others => '0');
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case rectype is
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when "0001" =>
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hread(L1, recaddr(15 downto 0));
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when "0010" =>
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hread(L1, recaddr(23 downto 0));
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when "0011" =>
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hread(L1, recaddr);
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when others => next;
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end case;
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hread(L1, recdata);
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recaddr(31 downto abits+2) := (others => '0');
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ai := conv_integer(recaddr)/4;
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for i in 0 to 3 loop
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ram(ai+i) <= recdata((i*32) to (i*32+31));
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end loop;
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if ai = 0 then
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ai := 1;
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end if;
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end if;
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end if;
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end if;
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end loop;
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FIRST := false;
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end if;
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end process RamProc;
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ramdata <= ram(to_integer(unsigned(read_address)));
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reg : process (clk)
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begin
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if rising_edge(clk) then
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r <= c;
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if RESET_ALL and rst = '0' then
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r <= RES;
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end if;
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end if;
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end process;
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bootmsg : report_version
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generic map ("ahbram" & tost(hindex) &
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": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
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end;
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-- pragma translate_on
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