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85 lines
2.5 KiB
VHDL
85 lines
2.5 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Delayed bidirectional wire
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity delay_wire is
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generic(
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data_width : integer := 1;
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delay_atob : real := 0.0;
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delay_btoa : real := 0.0
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);
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port(
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a : inout std_logic_vector(data_width-1 downto 0);
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b : inout std_logic_vector(data_width-1 downto 0);
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x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
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);
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end delay_wire;
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architecture rtl of delay_wire is
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signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
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constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
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function errinj(a,b: std_logic_vector) return std_logic_vector is
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variable r: std_logic_vector(a'length-1 downto 0);
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begin
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r := a;
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for k in a'length-1 downto 0 loop
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if (a(k)='0' or a(k)='1') and b(k)='1' then
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r(k) := not a(k);
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end if;
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end loop;
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return r;
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end;
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begin
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process(a)
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begin
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if a'event then
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if b_dly = zvector then
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a_dly <= transport a after delay_atob*1 ns;
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else
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a_dly <= (others => 'Z');
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end if;
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end if;
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end process;
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process(b)
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begin
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if b'event then
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if a_dly = zvector then
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b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
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else
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b_dly <= (others => 'Z');
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end if;
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end if;
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end process;
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a <= b_dly; b <= a_dly;
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end;
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