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73 lines
2.4 KiB
VHDL
73 lines
2.4 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: sram16
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-- File: sram16.vhd
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-- Author: Jiri Gaisler Gaisler Research
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-- Description: Simulation model of generic 16-bit async SRAM
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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library gaisler;
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use gaisler.sim.all;
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library grlib;
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use grlib.stdlib.all;
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entity sram16 is
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generic (
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index : integer := 0; -- Byte lane (0 - 3)
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abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
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echk : integer := 0; -- Generate EDAC checksum
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tacc : integer := 10; -- access time (ns)
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fname : string := "ram.dat"; -- File to read from
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clear : integer := 0); -- clear memory
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port (
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a : in std_logic_vector(abits-1 downto 0);
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d : inout std_logic_vector(15 downto 0);
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lb : in std_logic;
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ub : in std_logic;
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ce : in std_logic;
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we : in std_ulogic;
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oe : in std_ulogic);
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end;
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architecture sim of sram16 is
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signal cex : std_logic_vector(0 to 1);
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begin
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cex(0) <= ce or lb; cex(1) <= ce or ub;
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sr0 : sram generic map (index+1, abits, tacc, fname, clear)
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port map (a, d(7 downto 0), cex(0), we, oe);
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sr1 : sram generic map (index, abits, tacc, fname, clear)
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port map (a, d(15 downto 8), cex(1), we, oe);
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end sim;
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-- pragma translate_on
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