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98 lines
2.9 KiB
VHDL
98 lines
2.9 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Entity: spi2ahb
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-- File: spi2ahb.vhd
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-- Author: Jan Andersson - Aeroflex Gaisler AB
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-- Contact: support@gaisler.com
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-- Description: Simple SPI slave providing a bridge to AMBA AHB
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-- See spi2ahbx.vhd and GRIP for documentation
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.conv_std_logic_vector;
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library gaisler;
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use gaisler.spi.all;
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entity spi2ahb is
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generic (
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-- AHB Configuration
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hindex : integer := 0;
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--
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ahbaddrh : integer := 0;
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ahbaddrl : integer := 0;
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ahbmaskh : integer := 0;
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ahbmaskl : integer := 0;
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--
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oepol : integer range 0 to 1 := 0;
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--
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filter : integer range 2 to 512 := 2;
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--
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cpol : integer range 0 to 1 := 0;
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cpha : integer range 0 to 1 := 0
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);
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port (
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rstn : in std_ulogic;
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clk : in std_ulogic;
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-- AHB master interface
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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-- SPI signals
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spii : in spi_in_type;
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spio : out spi_out_type
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);
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end entity spi2ahb;
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architecture rtl of spi2ahb is
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signal spi2ahbi : spi2ahb_in_type;
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begin
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bridge : spi2ahbx
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generic map (
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hindex => hindex,
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oepol => oepol,
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filter => filter,
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cpol => cpol,
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cpha => cpha)
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port map (
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rstn => rstn,
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clk => clk,
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ahbi => ahbi,
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ahbo => ahbo,
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spii => spii,
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spio => spio,
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spi2ahbi => spi2ahbi,
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spi2ahbo => open);
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spi2ahbi.en <= '1';
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spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
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conv_std_logic_vector(ahbaddrl, 16);
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spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
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conv_std_logic_vector(ahbmaskl, 16);
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end architecture rtl;
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