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316 lines
12 KiB
VHDL
316 lines
12 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Entity: spictrl
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-- File: spictrl.vhd
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-- Author: Jan Andersson - Aeroflex Gaisler AB
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-- Contact: support@gaisler.com
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-- Description: Wrapper for SPICTRL core
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.netcomp.all;
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library grlib;
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use grlib.amba.all;
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use grlib.devices.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.spi.all;
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entity spictrl is
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generic (
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-- APB generics
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pindex : integer := 0; -- slave bus index
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paddr : integer := 0; -- APB address
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pmask : integer := 16#fff#; -- APB mask
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pirq : integer := 0; -- interrupt index
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-- SPI controller configuration
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fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
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slvselen : integer range 0 to 1 := 0; -- Slave select register enable
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slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
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oepol : integer range 0 to 1 := 0; -- Output enable polarity
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odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
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-- set if pads are i/o or od pads.
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automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
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acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
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aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
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twen : integer range 0 to 1 := 1; -- Enable three wire mode
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maxwlen : integer range 0 to 15 := 0; -- Maximum word length
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netlist : integer := 0; -- Use netlist (tech)
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syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
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memtech : integer := 0; -- Memory technology
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ft : integer range 0 to 2 := 0; -- Fault-Tolerance
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scantest : integer range 0 to 1 := 0; -- Scan test support
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syncrst : integer range 0 to 1 := 0; -- Use only sync reset
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automask0 : integer := 0; -- Mask 0 for automated transfers
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automask1 : integer := 0; -- Mask 1 for automated transfers
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automask2 : integer := 0; -- Mask 2 for automated transfers
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automask3 : integer := 0; -- Mask 3 for automated transfers
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ignore : integer range 0 to 1 := 0; -- Ignore samples
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prot : integer range 0 to 2 := 0 -- 0: Legacy, 1: dual, 2: quad
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);
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port (
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rstn : in std_ulogic;
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clk : in std_ulogic;
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-- APB signals
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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-- SPI signals
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spii : in spi_in_type;
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spio : out spi_out_type;
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slvsel : out std_logic_vector((slvselsz-1) downto 0)
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);
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end entity spictrl;
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architecture rtl of spictrl is
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-----------------------------------------------------------------------------
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-- Constants
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-----------------------------------------------------------------------------
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constant SPICTRL_REV : integer := 6;
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constant PCONFIG : apb_config_type := (
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0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, SPICTRL_REV, pirq),
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1 => apb_iobar(paddr, pmask));
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-----------------------------------------------------------------------------
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-- Component
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-----------------------------------------------------------------------------
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component spictrlx
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generic (
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rev : integer := 0;
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fdepth : integer range 1 to 7 := 1;
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slvselen : integer range 0 to 1 := 0;
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slvselsz : integer range 1 to 32 := 1;
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oepol : integer range 0 to 1 := 0;
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odmode : integer range 0 to 1 := 0;
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automode : integer range 0 to 1 := 0;
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acntbits : integer range 1 to 32 := 32;
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aslvsel : integer range 0 to 1 := 0;
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twen : integer range 0 to 1 := 1;
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maxwlen : integer range 0 to 15 := 0;
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syncram : integer range 0 to 1 := 1;
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memtech : integer range 0 to NTECH := 0;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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syncrst : integer range 0 to 1 := 0;
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automask0 : integer := 0;
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automask1 : integer := 0;
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automask2 : integer := 0;
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automask3 : integer := 0;
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ignore : integer range 0 to 1 := 0;
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prot : integer range 0 to 2 := 0);
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port (
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rstn : in std_ulogic;
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clk : in std_ulogic;
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-- APB signals
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apbi_psel : in std_ulogic;
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apbi_penable : in std_ulogic;
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apbi_paddr : in std_logic_vector(31 downto 0);
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apbi_pwrite : in std_ulogic;
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apbi_pwdata : in std_logic_vector(31 downto 0);
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apbi_testen : in std_ulogic;
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apbi_testrst : in std_ulogic;
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apbi_scanen : in std_ulogic;
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apbi_testoen : in std_ulogic;
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apbo_prdata : out std_logic_vector(31 downto 0);
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apbo_pirq : out std_ulogic;
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-- SPI signals
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spii_miso : in std_ulogic;
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spii_mosi : in std_ulogic;
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spii_sck : in std_ulogic;
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spii_spisel : in std_ulogic;
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spii_astart : in std_ulogic;
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spii_cstart : in std_ulogic;
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spii_ignore : in std_ulogic;
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spii_io2 : in std_ulogic;
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spii_io3 : in std_ulogic;
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spio_miso : out std_ulogic;
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spio_misooen : out std_ulogic;
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spio_mosi : out std_ulogic;
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spio_mosioen : out std_ulogic;
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spio_sck : out std_ulogic;
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spio_sckoen : out std_ulogic;
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spio_enable : out std_ulogic;
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spio_astart : out std_ulogic;
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spio_aready : out std_ulogic;
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spio_io2 : out std_ulogic;
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spio_io2oen : out std_ulogic;
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spio_io3 : out std_ulogic;
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spio_io3oen : out std_ulogic;
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slvsel : out std_logic_vector((slvselsz-1) downto 0));
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end component;
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal apbo_pirq : std_ulogic;
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begin
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ctrl_rtl : if netlist = 0 generate
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rtlc : spictrlx
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generic map (
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rev => SPICTRL_REV,
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fdepth => fdepth,
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slvselen => slvselen,
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slvselsz => slvselsz,
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oepol => oepol,
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odmode => odmode,
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automode => automode,
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acntbits => acntbits,
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aslvsel => aslvsel,
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twen => twen,
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maxwlen => maxwlen,
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syncram => syncram,
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memtech => memtech,
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ft => ft,
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scantest => scantest,
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syncrst => syncrst,
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automask0 => automask0,
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automask1 => automask1,
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automask2 => automask2,
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automask3 => automask3,
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ignore => ignore,
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prot => prot)
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port map (
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rstn => rstn,
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clk => clk,
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-- APB signals
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apbi_psel => apbi.psel(pindex),
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apbi_penable => apbi.penable,
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apbi_paddr => apbi.paddr,
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apbi_pwrite => apbi.pwrite,
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apbi_pwdata => apbi.pwdata,
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apbi_testen => apbi.testen,
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apbi_testrst => apbi.testrst,
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apbi_scanen => apbi.scanen,
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apbi_testoen => apbi.testoen,
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apbo_prdata => apbo.prdata,
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apbo_pirq => apbo_pirq,
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-- SPI signals
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spii_miso => spii.miso,
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spii_mosi => spii.mosi,
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spii_sck => spii.sck,
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spii_spisel => spii.spisel,
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spii_astart => spii.astart,
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spii_cstart => spii.cstart,
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spii_ignore => spii.ignore,
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spii_io2 => spii.io2,
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spii_io3 => spii.io3,
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spio_miso => spio.miso,
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spio_misooen => spio.misooen,
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spio_mosi => spio.mosi,
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spio_mosioen => spio.mosioen,
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spio_sck => spio.sck,
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spio_sckoen => spio.sckoen,
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spio_enable => spio.enable,
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spio_astart => spio.astart,
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spio_aready => spio.aready,
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spio_io2 => spio.io2,
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spio_io2oen => spio.io2oen,
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spio_io3 => spio.io3,
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spio_io3oen => spio.io3oen,
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slvsel => slvsel);
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end generate ctrl_rtl;
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ctrl_netlist : if netlist /= 0 generate
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netlc : spictrl_net
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generic map (
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tech => netlist,
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fdepth => fdepth,
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slvselen => slvselen,
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slvselsz => slvselsz,
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oepol => oepol,
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odmode => odmode,
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automode => automode,
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acntbits => acntbits,
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aslvsel => aslvsel,
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twen => twen,
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maxwlen => maxwlen,
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automask0 => automask0,
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automask1 => automask1,
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automask2 => automask2,
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automask3 => automask3)
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port map (
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rstn => rstn,
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clk => clk,
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-- APB signals
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apbi_psel => apbi.psel(pindex),
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apbi_penable => apbi.penable,
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apbi_paddr => apbi.paddr,
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apbi_pwrite => apbi.pwrite,
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apbi_pwdata => apbi.pwdata,
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apbi_testen => apbi.testen,
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apbi_testrst => apbi.testrst,
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apbi_scanen => apbi.scanen,
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apbi_testoen => apbi.testoen,
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apbo_prdata => apbo.prdata,
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apbo_pirq => apbo_pirq,
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-- SPI signals
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spii_miso => spii.miso,
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spii_mosi => spii.mosi,
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spii_sck => spii.sck,
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spii_spisel => spii.spisel,
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spii_astart => spii.astart,
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spii_cstart => spii.cstart,
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spio_miso => spio.miso,
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spio_misooen => spio.misooen,
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spio_mosi => spio.mosi,
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spio_mosioen => spio.mosioen,
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spio_sck => spio.sck,
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spio_sckoen => spio.sckoen,
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spio_enable => spio.enable,
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spio_astart => spio.astart,
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spio_aready => spio.aready,
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slvsel => slvsel);
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end generate ctrl_netlist;
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irqgen : process(apbo_pirq)
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variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
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begin
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irq := (others => '0'); irq(pirq) := apbo_pirq;
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apbo.pirq <= irq;
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end process;
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apbo.pconfig <= PCONFIG;
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apbo.pindex <= pindex;
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-- Boot message
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-- pragma translate_off
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bootmsg : report_version
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generic map (
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"spictrl" & tost(pindex) & ": SPI controller, rev " &
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tost(SPICTRL_REV) & ", irq " & tost(pirq));
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-- pragma translate_on
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end architecture rtl;
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