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54 lines
2 KiB
VHDL
54 lines
2 KiB
VHDL
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2017, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: dftlib
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-- File: dftlib.vhd
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-- Author: Magnus Hjorth - Aeroflex Gaisler
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-- Description: Package for ASIC design-for-test functionality
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package dftlib is
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-----------------------------------------------------------------------------
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-- Synchronous I/O test module
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-----------------------------------------------------------------------------
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component synciotest is
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generic (
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ninputs : integer;
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noutputs : integer;
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nbidir : integer;
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dirmode : integer := 0
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);
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port (
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clk: in std_ulogic;
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rstn: in std_ulogic;
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datain: in std_logic_vector(ninputs+nbidir-1 downto 0);
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dataout: out std_logic_vector(noutputs+nbidir-1 downto 0);
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tmode: in std_logic_vector(5 downto 0);
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tmodeact: out std_ulogic;
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tmodeoe: out std_ulogic
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);
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end component;
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end;
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