mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-23 21:17:07 -04:00
367 lines
14 KiB
VHDL
367 lines
14 KiB
VHDL
----------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2004 GAISLER RESEARCH
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-----------------------------------------------------------------------------
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-- Package: components
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-- File: components.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Component declaration of Micron SDRAM
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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package components is
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component mt48lc16m16a2
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GENERIC (
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-- Timing Parameters for -75 (PC133) and CAS Latency = 2
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tAC : TIME := 6.0 ns;
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tHZ : TIME := 7.0 ns;
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tOH : TIME := 2.7 ns;
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tMRD : INTEGER := 2; -- 2 Clk Cycles
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tRAS : TIME := 44.0 ns;
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tRC : TIME := 66.0 ns;
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tRCD : TIME := 20.0 ns;
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tRP : TIME := 20.0 ns;
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tRRD : TIME := 15.0 ns;
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tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
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tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
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tAH : TIME := 0.8 ns;
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tAS : TIME := 1.5 ns;
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tCH : TIME := 2.5 ns;
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tCL : TIME := 2.5 ns;
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tCK : TIME := 10.0 ns;
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tDH : TIME := 0.8 ns;
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tDS : TIME := 1.5 ns;
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tCKH : TIME := 0.8 ns;
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tCKS : TIME := 1.5 ns;
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tCMH : TIME := 0.8 ns;
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tCMS : TIME := 1.5 ns;
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addr_bits : INTEGER := 13;
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data_bits : INTEGER := 16;
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col_bits : INTEGER := 9;
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index : INTEGER := 0;
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fname : string := "ram.srec" -- File to read from
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);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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Ba : IN STD_LOGIC_VECTOR := "00";
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Clk : IN STD_LOGIC := '0';
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Cke : IN STD_LOGIC := '1';
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Cs_n : IN STD_LOGIC := '1';
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Ras_n : IN STD_LOGIC := '1';
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Cas_n : IN STD_LOGIC := '1';
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We_n : IN STD_LOGIC := '1';
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Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
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);
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end component;
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component mt46v16m16
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GENERIC ( -- Timing for -75Z CL2
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tCK : TIME := 7.500 ns;
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tCH : TIME := 3.375 ns; -- 0.45*tCK
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tCL : TIME := 3.375 ns; -- 0.45*tCK
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tDH : TIME := 0.500 ns;
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tDS : TIME := 0.500 ns;
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tIH : TIME := 0.900 ns;
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tIS : TIME := 0.900 ns;
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tMRD : TIME := 15.000 ns;
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tRAS : TIME := 40.000 ns;
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tRAP : TIME := 20.000 ns;
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tRC : TIME := 65.000 ns;
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tRFC : TIME := 75.000 ns;
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tRCD : TIME := 20.000 ns;
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tRP : TIME := 20.000 ns;
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tRRD : TIME := 15.000 ns;
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tWR : TIME := 15.000 ns;
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addr_bits : INTEGER := 13;
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data_bits : INTEGER := 16;
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cols_bits : INTEGER := 9;
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index : INTEGER := 0;
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fname : string := "ram.srec"; -- File to read from
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bbits : INTEGER := 16;
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fdelay : INTEGER := 0;
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chktiming : boolean := true
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);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
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Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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Clk : IN STD_LOGIC;
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Clk_n : IN STD_LOGIC;
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Cke : IN STD_LOGIC;
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Cs_n : IN STD_LOGIC;
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Ras_n : IN STD_LOGIC;
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Cas_n : IN STD_LOGIC;
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We_n : IN STD_LOGIC;
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Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
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);
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END component;
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component ftmt48lc16m16a2
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GENERIC (
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-- Timing Parameters for -75 (PC133) and CAS Latency = 2
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tAC : TIME := 6.0 ns;
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tHZ : TIME := 7.0 ns;
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tOH : TIME := 2.7 ns;
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tMRD : INTEGER := 2; -- 2 Clk Cycles
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tRAS : TIME := 44.0 ns;
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tRC : TIME := 66.0 ns;
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tRCD : TIME := 20.0 ns;
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tRP : TIME := 20.0 ns;
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tRRD : TIME := 15.0 ns;
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tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
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tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
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tAH : TIME := 0.8 ns;
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tAS : TIME := 1.5 ns;
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tCH : TIME := 2.5 ns;
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tCL : TIME := 2.5 ns;
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tCK : TIME := 10.0 ns;
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tDH : TIME := 0.8 ns;
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tDS : TIME := 1.5 ns;
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tCKH : TIME := 0.8 ns;
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tCKS : TIME := 1.5 ns;
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tCMH : TIME := 0.8 ns;
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tCMS : TIME := 1.5 ns;
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addr_bits : INTEGER := 13;
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data_bits : INTEGER := 16;
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col_bits : INTEGER := 9;
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index : INTEGER := 0;
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fname : string := "ram.srec"; -- File to read from
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err : INTEGER := 0
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);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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Ba : IN STD_LOGIC_VECTOR := "00";
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Clk : IN STD_LOGIC := '0';
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Cke : IN STD_LOGIC := '1';
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Cs_n : IN STD_LOGIC := '1';
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Ras_n : IN STD_LOGIC := '1';
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Cas_n : IN STD_LOGIC := '1';
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We_n : IN STD_LOGIC := '1';
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Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
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);
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end component;
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component ddr2 is
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generic(
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DM_BITS : integer := 2;
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ADDR_BITS : integer := 13;
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ROW_BITS : integer := 13;
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COL_BITS : integer := 9;
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DQ_BITS : integer := 16;
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DQS_BITS : integer := 2;
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TRRD : integer := 10000;
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TFAW : integer := 50000;
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DEBUG : integer := 0
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);
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port (
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ck : in std_ulogic;
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ck_n : in std_ulogic;
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cke : in std_ulogic;
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cs_n : in std_ulogic;
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ras_n : in std_ulogic;
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cas_n : in std_ulogic;
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we_n : in std_ulogic;
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dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
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ba : in std_logic_vector(1 downto 0);
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addr : in std_logic_vector(ADDR_BITS-1 downto 0);
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dq : inout std_logic_vector(DQ_BITS-1 downto 0);
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dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
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dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
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rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
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odt : in std_ulogic
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);
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end component;
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component mobile_ddr
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--GENERIC ( -- Timing for -75Z CL2
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-- tCK : TIME := 7.500 ns;
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-- tCH : TIME := 3.375 ns; -- 0.45*tCK
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-- tCL : TIME := 3.375 ns; -- 0.45*tCK
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-- tDH : TIME := 0.500 ns;
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-- tDS : TIME := 0.500 ns;
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-- tIH : TIME := 0.900 ns;
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-- tIS : TIME := 0.900 ns;
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-- tMRD : TIME := 15.000 ns;
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-- tRAS : TIME := 40.000 ns;
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-- tRAP : TIME := 20.000 ns;
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-- tRC : TIME := 65.000 ns;
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-- tRFC : TIME := 75.000 ns;
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-- tRCD : TIME := 20.000 ns;
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-- tRP : TIME := 20.000 ns;
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-- tRRD : TIME := 15.000 ns;
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-- tWR : TIME := 15.000 ns;
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-- addr_bits : INTEGER := 13;
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-- data_bits : INTEGER := 16;
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-- cols_bits : INTEGER := 9;
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-- index : INTEGER := 0;
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-- fname : string := "ram.srec"; -- File to read from
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-- bbits : INTEGER := 32
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--);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
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----Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
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----Dqs : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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----Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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Clk : IN STD_LOGIC;
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Clk_n : IN STD_LOGIC;
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Cke : IN STD_LOGIC;
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Cs_n : IN STD_LOGIC;
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Ras_n : IN STD_LOGIC;
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Cas_n : IN STD_LOGIC;
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We_n : IN STD_LOGIC;
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Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
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----Dm : IN STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
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);
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END component;
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component mobile_ddr_fe
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generic (addr_swap : integer := 0);
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port (
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Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
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Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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Clk : IN STD_LOGIC;
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Clk_n : IN STD_LOGIC;
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Cke : IN STD_LOGIC;
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Cs_n : IN STD_LOGIC;
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Ras_n : IN STD_LOGIC;
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Cas_n : IN STD_LOGIC;
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We_n : IN STD_LOGIC;
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Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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BEaddr: out std_logic_vector (24 downto 0);
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BEwr : out std_logic_vector(1 downto 0);
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BEdin : out std_logic_vector(15 downto 0);
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BEdout: in std_logic_vector(15 downto 0);
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BEclear: out std_logic;
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BEclrpart: out std_logic;
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BEsynco: out std_logic;
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BEsynci: in std_logic
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);
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end component;
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component mobile_ddr_febe
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generic (
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dbits: integer := 32;
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rampad: integer := 0;
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fname: string := "dummy";
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autoload: integer := 1;
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rstmode: integer := 0;
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rstdatah: integer := 16#DEAD#;
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rstdatal: integer := 16#BEEF#;
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addr_swap : integer := 0;
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offset_addr : std_logic_vector(31 downto 0) := x"00000000";
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swap_halfw : integer := 0
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);
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port (
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Dq : INOUT STD_LOGIC_VECTOR (dbits-1 DOWNTO 0) := (OTHERS => 'Z');
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Dqs : INOUT STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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Clk : IN STD_LOGIC;
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Clk_n : IN STD_LOGIC;
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Cke : IN STD_LOGIC;
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Cs_n : IN STD_LOGIC;
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Ras_n : IN STD_LOGIC;
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Cas_n : IN STD_LOGIC;
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We_n : IN STD_LOGIC;
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Dm : IN STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0)
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);
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end component;
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component mobile_ddr2_fe
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port (
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ck : in std_logic;
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ck_n : in std_logic;
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cke : in std_logic;
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cs_n : in std_logic;
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ca : in std_logic_vector( 9 downto 0);
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dm : in std_logic_vector( 1 downto 0);
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dq : inout std_logic_vector(15 downto 0) := (OTHERS => 'Z');
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dqs : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
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dqs_n : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
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BEaddr : out std_logic_vector(27 downto 0);
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BEwr_h : out std_logic_vector( 1 downto 0);
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BEwr_l : out std_logic_vector( 1 downto 0);
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BEdin_h : out std_logic_vector(15 downto 0);
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BEdin_l : out std_logic_vector(15 downto 0);
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BEdout_h: in std_logic_vector(15 downto 0);
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BEdout_l: in std_logic_vector(15 downto 0);
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BEclear : out std_logic;
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BEreload: out std_logic;
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BEsynco : out std_logic;
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BEsynci : in std_logic
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);
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end component;
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component mobile_ddr2_febe
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generic (
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dbits: integer := 32;
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rampad: integer := 0;
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fname: string := "dummy";
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autoload: integer := 1;
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rstmode: integer := 0;
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rstdatah: integer := 16#DEAD#;
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rstdatal: integer := 16#BEEF#
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);
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port (
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ck : in std_logic;
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ck_n : in std_logic;
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cke : in std_logic;
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cs_n : in std_logic;
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ca : in std_logic_vector( 9 downto 0);
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dm : in std_logic_vector(dbits/8-1 downto 0);
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dq : inout std_logic_vector( dbits-1 downto 0) := (OTHERS => 'Z');
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dqs : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z');
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dqs_n : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z')
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);
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end component;
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component mobile_sdr
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--GENERIC (
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-- DEBUG : INTEGER := 1;
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-- addr_bits : INTEGER := 13;
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-- data_bits : INTEGER := 16
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--);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
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Ba : IN STD_LOGIC_VECTOR := "00";
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Clk : IN STD_LOGIC := '0';
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Cke : IN STD_LOGIC := '1';
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Cs_n : IN STD_LOGIC := '1';
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Ras_n : IN STD_LOGIC := '1';
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Cas_n : IN STD_LOGIC := '1';
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We_n : IN STD_LOGIC := '1';
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Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
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);
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end component;
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end;
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-- pragma translate_on
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