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https://github.com/lcbcFoo/ReonV.git
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111 lines
3.4 KiB
VHDL
111 lines
3.4 KiB
VHDL
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----------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2010 Aeroflex Gaisler
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----------------------------------------------------------------------------
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-- Entity: ahbrom
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-- File: ahbrom.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Modified Alen Bardizbanyan - Cobham Gaisler (pipelined impl.)
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-- Description: AHB rom. 0/1-waitstate read
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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use grlib.config_types.all;
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use grlib.config.all;
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entity ahbrom is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#fff#;
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pipe : integer := 0;
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tech : integer := 0;
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kbytes : integer := 1);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end;
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architecture rtl of ahbrom is
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constant abits : integer := 5;
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constant bytes : integer := 20;
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constant dbits : integer := 32;
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constant hconfig : ahb_config_type := (
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0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
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4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
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signal romdata : std_logic_vector(dbits-1 downto 0);
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signal romdatas : std_logic_vector(AHBDW-1 downto 0);
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signal addr : std_logic_vector(abits-1 downto 2);
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signal hsize : std_logic_vector(2 downto 0);
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signal romaddr : std_logic_vector(abits-1 downto log2(dbits/8));
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signal hready, active : std_ulogic;
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constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
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begin
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ahbso.hresp <= "00";
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ahbso.hsplit <= (others => '0');
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ahbso.hirq <= (others => '0');
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ahbso.hconfig <= hconfig;
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ahbso.hindex <= hindex;
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reg : process (clk)
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begin
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if rising_edge(clk) then
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addr <= ahbsi.haddr(abits-1 downto 2);
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hsize <= ahbsi.hsize;
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if RESET_ALL and rst='0' then addr <= (others => '0'); hsize <= "000"; end if;
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end if;
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end process;
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p0 : if pipe = 0 generate
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ahbso.hrdata <= romdatas;
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ahbso.hready <= '1';
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hready <= '0';
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end generate;
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active <= ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready;
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p1 : if pipe = 1 generate
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ahbso.hready <= hready;
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reg2 : process (clk)
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begin
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if rising_edge(clk) then
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hready <= (not rst) or (not active) or (not(hready));
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ahbso.hrdata <= romdatas;
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if RESET_ALL and rst='0' then hready <= '1'; ahbso.hrdata <= (others => '0'); end if;
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end if;
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end process;
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end generate;
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romaddr <= addr(abits-1 downto log2(dbits/8));
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romdatas <= ahbdrivedata(romdata);
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comb : process (romaddr)
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begin
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case conv_integer(romaddr) is
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when 16#00000# => romdata <= X"37010048";
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when 16#00001# => romdata <= X"130101fe";
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when 16#00002# => romdata <= X"b7070040";
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when 16#00003# => romdata <= X"e7800700";
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when 16#00004# => romdata <= X"13000000";
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when 16#00005# => romdata <= X"00000000";
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when others => romdata <= (others => '-');
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end case;
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end process;
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-- pragma translate_off
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bootmsg : report_version
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generic map ("ahbrom" & tost(hindex) &
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": 32-bit AHB ROM Module, " & tost(bytes/(dbits/8)) & " words, " & tost(abits-log2(dbits/8)) & " address bits" );
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-- pragma translate_on
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end;
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