ReonV/designs/leon3-digilent-nexys4ddr/ahbrom.vhd
2018-01-18 14:48:40 -02:00

111 lines
3.4 KiB
VHDL

----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified Alen Bardizbanyan - Cobham Gaisler (pipelined impl.)
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 5;
constant bytes : integer := 20;
constant dbits : integer := 32;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(dbits-1 downto 0);
signal romdatas : std_logic_vector(AHBDW-1 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsize : std_logic_vector(2 downto 0);
signal romaddr : std_logic_vector(abits-1 downto log2(dbits/8));
signal hready, active : std_ulogic;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
hsize <= ahbsi.hsize;
if RESET_ALL and rst='0' then addr <= (others => '0'); hsize <= "000"; end if;
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdatas;
ahbso.hready <= '1';
hready <= '0';
end generate;
active <= ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready;
p1 : if pipe = 1 generate
ahbso.hready <= hready;
reg2 : process (clk)
begin
if rising_edge(clk) then
hready <= (not rst) or (not active) or (not(hready));
ahbso.hrdata <= romdatas;
if RESET_ALL and rst='0' then hready <= '1'; ahbso.hrdata <= (others => '0'); end if;
end if;
end process;
end generate;
romaddr <= addr(abits-1 downto log2(dbits/8));
romdatas <= ahbdrivedata(romdata);
comb : process (romaddr)
begin
case conv_integer(romaddr) is
when 16#00000# => romdata <= X"37010048";
when 16#00001# => romdata <= X"130101fe";
when 16#00002# => romdata <= X"b7070040";
when 16#00003# => romdata <= X"e7800700";
when 16#00004# => romdata <= X"13000000";
when 16#00005# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/(dbits/8)) & " words, " & tost(abits-log2(dbits/8)) & " address bits" );
-- pragma translate_on
end;