mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-24 22:17:05 -04:00
Remove INSTRUCTION_READY
Add proper Fetcher.ibusRsp.flush prediction are disabled yet much is broken for sure, WIP
This commit is contained in:
Charles Papon
parent
f1959ff830
commit
29f85a7ae2
5 changed files with 237 additions and 256 deletions
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@ -36,7 +36,6 @@ case class VexRiscvConfig(){
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object PC extends Stageable(UInt(32 bits))
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object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits))
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object INSTRUCTION extends Stageable(Bits(32 bits))
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object INSTRUCTION_READY extends Stageable(Bool)
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object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))
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object LEGAL_INSTRUCTION extends Stageable(Bool)
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object REGFILE_WRITE_VALID extends Stageable(Bool)
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@ -172,7 +172,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
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}
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if(catchIllegalInstruction){
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decodeExceptionPort.valid := arbitration.isValid && input(INSTRUCTION_READY) && !input(LEGAL_INSTRUCTION) // ?? HalitIt to alow decoder stage to wait valid data from 2 stages cache cache ??
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decodeExceptionPort.valid := arbitration.isValid && !input(LEGAL_INSTRUCTION) // ?? HalitIt to alow decoder stage to wait valid data from 2 stages cache cache ??
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decodeExceptionPort.code := 2
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decodeExceptionPort.badAddr := input(INSTRUCTION).asUInt
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}
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@ -67,29 +67,42 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pipeline(RVC_GEN) = compressedGen
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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case DYNAMIC_TARGET => {
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fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
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if(compressedGen && cmdToRspStageCount > 1){
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dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode)
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}
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}
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}
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// prediction match {
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// case NONE =>
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// case STATIC | DYNAMIC => {
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// predictionJumpInterface = createJumpInterface(pipeline.decode)
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// decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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// }
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// case DYNAMIC_TARGET => {
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// fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
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// if(compressedGen && cmdToRspStageCount > 1){
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// dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode)
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// }
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// }
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// }
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pcValids = Vec(Bool, pipeline.stages.size)
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}
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object IBUS_RSP
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object DECOMPRESSOR
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object INJECTOR_M2S
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def isDrivingDecode(s : Any): Boolean = {
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if(injectorStage) return s == INJECTOR_M2S
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if(compressedGen) return s == DECOMPRESSOR
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s == IBUS_RSP
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}
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def getFlushAt(s : Any, lastCond : Boolean = true): Bool = {
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if(isDrivingDecode(s) && lastCond) pipeline.decode.arbitration.isRemoved else fetcherflushIt
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}
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class FetchArea(pipeline : VexRiscv) extends Area {
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import pipeline._
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import pipeline.config._
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//JumpService hardware implementation
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//Arbitrate jump requests into pcLoad
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val jump = new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => {
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(pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) ||
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@ -117,25 +130,25 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val booted = RegNext(True) init (False)
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val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready)
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val pc = pcReg + (inc ## B"00").asUInt
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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// val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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if(compressedGen) when(inc) {
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pc(1) := False
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}
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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corrected := True
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pc := predictionPcLoad.payload
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}
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}
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// if(predictionPcLoad != null) {
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// when(predictionPcLoad.valid) {
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// corrected := True
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// pc := predictionPcLoad.payload
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// }
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// }
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when(jump.pcLoad.valid) {
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corrected := True
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pc := jump.pcLoad.payload
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}
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when(booted && (output.ready || fetcherflushIt || pcRegPropagate)){
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when(booted && (output.ready || corrected || pcRegPropagate)){
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pcReg := pc
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}
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@ -160,12 +173,12 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pcReg := pcPlus
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}
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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if(prediction == DYNAMIC_TARGET) {
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when(predictionPcLoad.valid) {
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pcReg := predictionPcLoad.payload
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}
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}
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// val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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// if(prediction == DYNAMIC_TARGET) {
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// when(predictionPcLoad.valid) {
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// pcReg := predictionPcLoad.payload
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// }
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// }
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//application of the selected jump request
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when(jump.pcLoad.valid && (!decode.arbitration.isStuck || decode.arbitration.isRemoved)) {
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@ -177,27 +190,18 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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case class FetchRsp() extends Bundle {
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val pc = UInt(32 bits)
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val rsp = IBusSimpleRsp()
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val isRvc = Bool
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val isRvc = Bool()
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}
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val iBusRsp = new Area {
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// val input = Stream(UInt(32 bits))
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// val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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// val inputPipelineHalt = Vec(False, cmdToRspStageCount-1)
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// for(i <- 0 until cmdToRspStageCount) {
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// inputPipeline(i) << {i match {
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// case 0 => input.m2sPipeWithFlush(flush, false, collapsBubble = false)
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// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false)
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// }}
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// }
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// val stages = Array.fill(cmdToRspStageCount)(Stream(UInt(32 bits)))
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val fetchFlush = False
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val stages = Array.fill(cmdToRspStageCount + 1)(new Bundle {
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val input = Stream(UInt(32 bits))
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val output = Stream(UInt(32 bits))
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val halt = Bool
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val inputSample = Bool
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val halt = Bool()
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val inputSample = Bool()
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val flush = Bool()
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})
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stages(0).input << fetchPc.output
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@ -207,29 +211,18 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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s.output << s.input.haltWhen(s.halt)
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}
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stages.head.flush := getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
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for((s,sNext) <- (stages, stages.tail).zipped) {
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sNext.flush := getFlushAt(IBUS_RSP, sNext == stages.last) || fetchFlush
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if(s == stages.head && pcRegReusedForSecondStage) {
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false))
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNext.flush, s != stages.head, collapsBubble = false))
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sNext.input.payload := fetchPc.pcReg
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fetchPc.pcRegPropagate setWhen(sNext.input.ready)
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} else {
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sNext.input << s.output.m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false)
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sNext.input << s.output.m2sPipeWithFlush(sNext.flush, s != stages.head, collapsBubble = false)
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}
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}
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//
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// val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount + 1)
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// val halts = Vec(False, cmdToRspStageCount)
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// for(i <- 0 until cmdToRspStageCount + 1) {
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// pipeline(i) << {i match {
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// case 0 => pipeline(0) << fetchPc.output.haltWhen(halts(i))
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// case 1 => pipeline(1).m2sPipeWithFlush(flush, false, collapsBubble = false)
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// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false)
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// }}
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// }
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// ...
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val readyForError = True
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val output = Stream(FetchRsp())
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incomingInstruction setWhen(stages.tail.map(_.input.valid).reduce(_ || _))
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@ -253,7 +246,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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output.pc := input.pc
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output.isRvc := isRvc
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output.rsp.inst := isRvc ? decompressed | raw
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// input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
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input.ready := !output.valid || !(!output.ready || (isRvc && !input.pc(1) && input.rsp.inst(16, 2 bits) =/= 3) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))
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addPrePopTask(() => {
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when(!input.ready && output.fire && !fetcherflushIt /* && ((isRvc && !bufferValid && !input.pc(1)) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))*/) {
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@ -286,7 +278,8 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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incomingInstruction setWhen (inputBeforeStage.valid)
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}
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val decodeInput = (if (injectorStage) {
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(fetcherflushIt, collapsBubble = false)
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val flushStage = getFlushAt(INJECTOR_M2S)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer
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incomingInstruction setWhen (decodeInput.valid)
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@ -323,13 +316,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pcValids := Vec(valids.takeRight(stages.size))
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}
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val decodeRemoved = RegInit(False) setWhen(decode.arbitration.isRemoved) clearWhen(fetcherflushIt) //!decode.arbitration.isStuck || decode.arbitration.isFlushed
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decodeInput.ready := !decode.arbitration.isStuck
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decode.arbitration.isValid := decodeInput.valid && !decodeRemoved
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decode.arbitration.isValid := decodeInput.valid
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decode.insert(PC) := (if (decodePcGen) decodePc.pcReg else decodeInput.pc)
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decode.insert(INSTRUCTION) := decodeInput.rsp.inst
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decode.insert(INSTRUCTION_READY) := True
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if (compressedGen) decode.insert(IS_RVC) := decodeInput.isRvc
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if (injectionPort != null) {
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@ -401,11 +391,11 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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else
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decode.input(PC) + 4)
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if(decodePc != null && decodePc.predictionPcLoad != null){
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when(decodePc.predictionPcLoad.valid){
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decode.insert(FORMAL_PC_NEXT) := decodePc.predictionPcLoad.payload
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}
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}
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// if(decodePc != null && decodePc.predictionPcLoad != null){
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// when(decodePc.predictionPcLoad.valid){
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// decode.insert(FORMAL_PC_NEXT) := decodePc.predictionPcLoad.payload
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// }
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// }
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jumpInfos.foreach(info => {
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when(info.interface.valid) {
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@ -429,182 +419,182 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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(ifGen(compressedGen)(decompressorContext), injectorContextWire)
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}
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val predictor = prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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def historyWidth = 2
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val dynamic = ifGen(prediction == DYNAMIC) (new Area {
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case class BranchPredictorLine() extends Bundle{
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val history = SInt(historyWidth bits)
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}
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val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = historyCache.writePort
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
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case class DynamicContext() extends Bundle{
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val hazard = Bool
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val line = BranchPredictorLine()
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}
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val fetchContext = DynamicContext()
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fetchContext.hazard := hazard
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb
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val branchStage = decodePrediction.stage
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val branchContext = branchStage.input(PREDICTION_CONTEXT)
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val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb
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historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN))
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((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0))
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else
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U(0))
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historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1))
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val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue)))
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historyWrite.valid := !branchContext.hazard && branchStage.arbitration.isFiring && branchStage.input(BRANCH_CTRL) === BranchCtrlEnum.B && !sat
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})
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val imm = IMM(decode.input(INSTRUCTION))
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val conditionalBranchPrediction = prediction match {
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case STATIC => imm.b_sext.msb
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case DYNAMIC => dynamic.decodeContextPrediction
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}
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decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
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val noPredictionOnMissaligned = (!pipeline(RVC_GEN)) generate new Area{
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val missaligned = decode.input(BRANCH_CTRL).mux(
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BranchCtrlEnum.JAL -> imm.j_sext(1),
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default -> imm.b_sext(1)
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)
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decodePrediction.cmd.hadBranch clearWhen(missaligned)
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}
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//TODO no more fireing depedancies
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predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité
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predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload)
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when(predictionJumpInterface.valid && decode.arbitration.isFiring){
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flushIt()
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}
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}
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case DYNAMIC_TARGET => new Area{
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// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air")
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case class BranchPredictorLine() extends Bundle{
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val source = Bits(30 - historyRamSizeLog2 bits)
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val branchWish = UInt(2 bits)
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val target = UInt(32 bits)
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val unaligned = ifGen(compressedGen)(Bool)
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}
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = history.writePort
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
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//Avoid stoping instruction fetch in the middle patch
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if(compressedGen && cmdToRspStageCount == 1){
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hit clearWhen(!decompressor.output.valid)
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}
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//Avoid write to read hazard
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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//TODO improve predictionPcLoad way of doing things
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.valid //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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fetchPc.predictionPcLoad.payload := line.target
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case class PredictionResult() extends Bundle{
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val hazard = Bool
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val hit = Bool
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val line = BranchPredictorLine()
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}
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val fetchContext = PredictionResult()
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fetchContext.hazard := hazard
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fetchContext.hit := hit
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fetchContext.line := line
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val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
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if(compressedGen) {
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//prediction hit on the right instruction into words
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decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1))))
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// if(compressedGen) injectorContext.hit clearWhen(decodePc.pcReg(1) =/= injectorContext.line.unaligned)
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decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
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decodePc.predictionPcLoad.payload := injectorContext.line.target
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when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
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decompressor.bufferValid := False
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decompressor.input.ready := True
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}
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}
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object PREDICTION_CONTEXT extends Stageable(PredictionResult())
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pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
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val branchStage = fetchPrediction.stage
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val branchContext = branchStage.input(PREDICTION_CONTEXT)
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|
||||
fetchPrediction.cmd.hadBranch := branchContext.hit && !branchContext.hazard && branchContext.line.branchWish.msb
|
||||
fetchPrediction.cmd.targetPc := branchContext.line.target
|
||||
|
||||
|
||||
historyWrite.valid := False
|
||||
historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits)
|
||||
historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2
|
||||
historyWrite.data.target := fetchPrediction.rsp.finalPc
|
||||
if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC)
|
||||
|
||||
when(fetchPrediction.rsp.wasRight) {
|
||||
historyWrite.valid := branchContext.hit
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish + (branchContext.line.branchWish === 2).asUInt - (branchContext.line.branchWish === 1).asUInt
|
||||
} otherwise {
|
||||
when(branchContext.hit) {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish - (branchContext.line.branchWish.msb).asUInt + (!branchContext.line.branchWish.msb).asUInt
|
||||
} otherwise {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := "10"
|
||||
}
|
||||
}
|
||||
|
||||
historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
|
||||
|
||||
|
||||
|
||||
val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{
|
||||
val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
|
||||
val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
|
||||
val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
|
||||
val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
|
||||
val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
|
||||
|
||||
dynamicTargetFailureCorrection.valid := False
|
||||
dynamicTargetFailureCorrection.payload := decode.input(PC)
|
||||
when(injectorFailure || bypassFailure){
|
||||
historyWrite.valid := True
|
||||
historyWrite.address := (decode.input(PC) >> 2).resized
|
||||
historyWrite.data.branchWish := 0
|
||||
|
||||
decode.arbitration.isValid := False
|
||||
decode.arbitration.flushNext := True
|
||||
dynamicTargetFailureCorrection.valid := True
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
// val predictor = prediction match {
|
||||
// case NONE =>
|
||||
// case STATIC | DYNAMIC => {
|
||||
// def historyWidth = 2
|
||||
// val dynamic = ifGen(prediction == DYNAMIC) (new Area {
|
||||
// case class BranchPredictorLine() extends Bundle{
|
||||
// val history = SInt(historyWidth bits)
|
||||
// }
|
||||
//
|
||||
// val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
|
||||
// val historyWrite = historyCache.writePort
|
||||
// val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
|
||||
// val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
|
||||
//
|
||||
// case class DynamicContext() extends Bundle{
|
||||
// val hazard = Bool
|
||||
// val line = BranchPredictorLine()
|
||||
// }
|
||||
// val fetchContext = DynamicContext()
|
||||
// fetchContext.hazard := hazard
|
||||
// fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
|
||||
//
|
||||
// object PREDICTION_CONTEXT extends Stageable(DynamicContext())
|
||||
// decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
|
||||
// val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb
|
||||
//
|
||||
// val branchStage = decodePrediction.stage
|
||||
// val branchContext = branchStage.input(PREDICTION_CONTEXT)
|
||||
// val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb
|
||||
//
|
||||
// historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN))
|
||||
// ((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0))
|
||||
// else
|
||||
// U(0))
|
||||
//
|
||||
// historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1))
|
||||
// val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue)))
|
||||
// historyWrite.valid := !branchContext.hazard && branchStage.arbitration.isFiring && branchStage.input(BRANCH_CTRL) === BranchCtrlEnum.B && !sat
|
||||
// })
|
||||
//
|
||||
//
|
||||
// val imm = IMM(decode.input(INSTRUCTION))
|
||||
//
|
||||
// val conditionalBranchPrediction = prediction match {
|
||||
// case STATIC => imm.b_sext.msb
|
||||
// case DYNAMIC => dynamic.decodeContextPrediction
|
||||
// }
|
||||
//
|
||||
// decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
|
||||
//
|
||||
// val noPredictionOnMissaligned = (!pipeline(RVC_GEN)) generate new Area{
|
||||
// val missaligned = decode.input(BRANCH_CTRL).mux(
|
||||
// BranchCtrlEnum.JAL -> imm.j_sext(1),
|
||||
// default -> imm.b_sext(1)
|
||||
// )
|
||||
// decodePrediction.cmd.hadBranch clearWhen(missaligned)
|
||||
// }
|
||||
//
|
||||
// //TODO no more fireing depedancies
|
||||
// predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité
|
||||
// predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
|
||||
// if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload)
|
||||
//
|
||||
// when(predictionJumpInterface.valid && decode.arbitration.isFiring){
|
||||
// flushIt()
|
||||
// }
|
||||
// }
|
||||
// case DYNAMIC_TARGET => new Area{
|
||||
//// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air")
|
||||
//
|
||||
// case class BranchPredictorLine() extends Bundle{
|
||||
// val source = Bits(30 - historyRamSizeLog2 bits)
|
||||
// val branchWish = UInt(2 bits)
|
||||
// val target = UInt(32 bits)
|
||||
// val unaligned = ifGen(compressedGen)(Bool)
|
||||
// }
|
||||
//
|
||||
// val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
|
||||
// val historyWrite = history.writePort
|
||||
//
|
||||
// val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
|
||||
// val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
|
||||
//
|
||||
// //Avoid stoping instruction fetch in the middle patch
|
||||
// if(compressedGen && cmdToRspStageCount == 1){
|
||||
// hit clearWhen(!decompressor.output.valid)
|
||||
// }
|
||||
//
|
||||
// //Avoid write to read hazard
|
||||
// val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
|
||||
// val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
|
||||
// //TODO improve predictionPcLoad way of doing things
|
||||
// fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.valid //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
|
||||
// fetchPc.predictionPcLoad.payload := line.target
|
||||
//
|
||||
// case class PredictionResult() extends Bundle{
|
||||
// val hazard = Bool
|
||||
// val hit = Bool
|
||||
// val line = BranchPredictorLine()
|
||||
// }
|
||||
//
|
||||
// val fetchContext = PredictionResult()
|
||||
// fetchContext.hazard := hazard
|
||||
// fetchContext.hit := hit
|
||||
// fetchContext.line := line
|
||||
//
|
||||
// val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
|
||||
// if(compressedGen) {
|
||||
// //prediction hit on the right instruction into words
|
||||
// decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1))))
|
||||
//
|
||||
// // if(compressedGen) injectorContext.hit clearWhen(decodePc.pcReg(1) =/= injectorContext.line.unaligned)
|
||||
//
|
||||
// decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
|
||||
// decodePc.predictionPcLoad.payload := injectorContext.line.target
|
||||
//
|
||||
//
|
||||
// when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
|
||||
// decompressor.bufferValid := False
|
||||
// decompressor.input.ready := True
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// object PREDICTION_CONTEXT extends Stageable(PredictionResult())
|
||||
// pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
|
||||
// val branchStage = fetchPrediction.stage
|
||||
// val branchContext = branchStage.input(PREDICTION_CONTEXT)
|
||||
//
|
||||
// fetchPrediction.cmd.hadBranch := branchContext.hit && !branchContext.hazard && branchContext.line.branchWish.msb
|
||||
// fetchPrediction.cmd.targetPc := branchContext.line.target
|
||||
//
|
||||
//
|
||||
// historyWrite.valid := False
|
||||
// historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits)
|
||||
// historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2
|
||||
// historyWrite.data.target := fetchPrediction.rsp.finalPc
|
||||
// if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC)
|
||||
//
|
||||
// when(fetchPrediction.rsp.wasRight) {
|
||||
// historyWrite.valid := branchContext.hit
|
||||
// historyWrite.data.branchWish := branchContext.line.branchWish + (branchContext.line.branchWish === 2).asUInt - (branchContext.line.branchWish === 1).asUInt
|
||||
// } otherwise {
|
||||
// when(branchContext.hit) {
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.data.branchWish := branchContext.line.branchWish - (branchContext.line.branchWish.msb).asUInt + (!branchContext.line.branchWish.msb).asUInt
|
||||
// } otherwise {
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.data.branchWish := "10"
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
|
||||
//
|
||||
//
|
||||
//
|
||||
// val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{
|
||||
// val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
|
||||
// val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
|
||||
// val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
|
||||
// val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
|
||||
// val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
|
||||
//
|
||||
// dynamicTargetFailureCorrection.valid := False
|
||||
// dynamicTargetFailureCorrection.payload := decode.input(PC)
|
||||
// when(injectorFailure || bypassFailure){
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.address := (decode.input(PC) >> 2).resized
|
||||
// historyWrite.data.branchWish := 0
|
||||
//
|
||||
// decode.arbitration.isValid := False
|
||||
// decode.arbitration.flushNext := True
|
||||
// dynamicTargetFailureCorrection.valid := True
|
||||
// }
|
||||
// })
|
||||
// }
|
||||
// }
|
||||
|
||||
def stageXToIBusRsp[T <: Data](stage : Any, input : T): (T) ={
|
||||
iBusRsp.stages.dropWhile(_ != stage).tail.foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
|
||||
|
|
|
|||
|
|
@ -237,19 +237,10 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
|
|||
decodeExceptionPort.code := 1
|
||||
}
|
||||
|
||||
when(!iBusRsp.readyForError){
|
||||
redoFetch := False
|
||||
cache.io.cpu.fill.valid := False
|
||||
}
|
||||
// when(pipeline.stages.map(_.arbitration.flushIt).orR){
|
||||
// cache.io.cpu.fill.valid := False
|
||||
// }
|
||||
|
||||
|
||||
|
||||
redoBranch.valid := redoFetch
|
||||
redoBranch.payload := (if (decodePcGen) decode.input(PC) else cacheRsp.pc)
|
||||
decode.arbitration.flushNext setWhen(redoBranch.valid)
|
||||
iBusRsp.fetchFlush setWhen(redoBranch.valid)
|
||||
|
||||
|
||||
cacheRspArbitration.halt setWhen (issueDetected || iBusRspOutputHalt)
|
||||
|
|
|
|||
|
|
@ -384,6 +384,7 @@ class IBusSimplePlugin( resetVector : BigInt,
|
|||
|
||||
decode.arbitration.flushIt setWhen(redoBranch.valid)
|
||||
decode.arbitration.flushNext setWhen(redoBranch.valid)
|
||||
???
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue