github-mirrors/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-06-27 17:01:02 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update README.md
Some checks failed
Scala CI / build (push) Has been cancelled
Details

Browse source
This commit is contained in:
Dolu1990 2025-01-24 10:37:49 +01:00
parent 7f2bccbef2
commit 35402a2bde
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -87,6 +87,8 @@ There is a gitter channel for all questions about VexRiscv :<br>
For commercial support, please contact spinalhdl@gmail.com.
Note you may be interested VexiiRiscv (https://github.com/SpinalHDL/VexiiRiscv).
## Area usage and maximal frequency
The following numbers were obtained by synthesizing the CPU as toplevel on the fastest speed grade without any specific synthesis options to save area or to get better maximal frequency (neutral).<br>