mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-24 05:57:07 -04:00
Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions
This commit is contained in:
Charles Papon
parent
eecc1e6b18
commit
62a55c4cf4
4 changed files with 100 additions and 44 deletions
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@ -13,10 +13,12 @@ case class DBusSimpleCmd() extends Bundle{
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}
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case class DBusSimpleRsp() extends Bundle{
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val ready = Bool
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val error = Bool
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val data = Bits(32 bit)
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}
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class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRiscv]{
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class DBusSimplePlugin(catchUnalignedException : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
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var dCmd : Stream[DBusSimpleCmd] = null
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var dRsp : DBusSimpleRsp = null
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@ -31,7 +33,7 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
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object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
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var executeExceptionPort : Flow[ExceptionCause] = null
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var memoryExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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import pipeline.config._
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@ -39,11 +41,12 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
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val decoderService = pipeline.service(classOf[DecoderService])
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val stdActions = List[(Stageable[_ <: BaseType],Any)](
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LEGAL_INSTRUCTION -> True,
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC_USE_SUB_LESS -> False,
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MEMORY_ENABLE -> True,
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REG1_USE -> True
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LEGAL_INSTRUCTION -> True,
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC_USE_SUB_LESS -> False,
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MEMORY_ENABLE -> True,
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REG1_USE -> True,
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IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB //Used for assess fault bad address in memory stage
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)
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val loadActions = stdActions ++ List(
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@ -75,6 +78,11 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
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val exceptionService = pipeline.service(classOf[ExceptionService])
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executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
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}
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if(catchAccessFault) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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memoryExceptionPort = exceptionService.newExceptionPort(pipeline.memory)
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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@ -115,7 +123,15 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
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dRsp = in(DBusSimpleRsp()).setName("dRsp")
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insert(MEMORY_READ_DATA) := dRsp.data
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assert(!(input(MEMORY_ENABLE) && (!input(INSTRUCTION)(5)) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
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arbitration.haltIt setWhen(arbitration.isValid && input(MEMORY_ENABLE) && !dRsp.ready)
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if(catchAccessFault){
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memoryExceptionPort.valid := arbitration.isValid && input(MEMORY_ENABLE) && dRsp.ready && dRsp.error
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memoryExceptionPort.code := 5
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memoryExceptionPort.badAddr := input(REGFILE_WRITE_DATA).asUInt //Drived by IntAluPlugin
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}
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assert(!(dRsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
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}
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//Reformat read responses, REGFILE_WRITE_DATA overriding
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@ -1,6 +1,6 @@
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package SpinalRiscv.Plugin
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import SpinalRiscv.VexRiscv
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import SpinalRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv}
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import spinal.core._
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import spinal.lib._
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@ -10,15 +10,24 @@ case class IBusSimpleCmd() extends Bundle{
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}
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case class IBusSimpleRsp() extends Bundle{
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val inst = Bits(32 bits)
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val ready = Bool
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val error = Bool
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val inst = Bits(32 bits)
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}
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class IBusSimplePlugin(interfaceKeepData : Boolean) extends Plugin[VexRiscv]{
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class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
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var iCmd : Stream[IBusSimpleCmd] = null
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var iRsp : IBusSimpleRsp = null
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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pipeline.unremovableStages += pipeline.prefetch
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if(catchAccessFault) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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@ -35,5 +44,13 @@ class IBusSimplePlugin(interfaceKeepData : Boolean) extends Plugin[VexRiscv]{
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//Insert iRsp into INSTRUCTION
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iRsp = in(IBusSimpleRsp()).setName("iRsp")
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fetch.insert(INSTRUCTION) := iRsp.inst
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fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iRsp.ready)
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fetch.insert(IBUS_ACCESS_ERROR) := iRsp.error
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if(catchAccessFault){
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decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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decodeExceptionPort.code := 1
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decodeExceptionPort.badAddr := decode.input(PC)
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}
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}
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}
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@ -70,7 +70,8 @@ object TopLevel {
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config.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true
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interfaceKeepData = true,
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catchAccessFault = true
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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@ -84,7 +85,8 @@ object TopLevel {
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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new DBusSimplePlugin(
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catchUnalignedException = true
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catchUnalignedException = true,
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catchAccessFault = true
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),
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new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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@ -204,6 +204,11 @@ public:
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top->reset = 0;
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top->iCmd_ready = 1;
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top->dCmd_ready = 1;
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top->iRsp_ready = 1;
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top->dRsp_ready = 1;
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top->iRsp_error = 0;
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top->dRsp_error = 0;
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top->eval(); currentTime = 3;
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top->reset = 1;
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top->eval();
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@ -214,7 +219,7 @@ public:
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dump(0);
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top->reset = 0;
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top->eval(); currentTime = 2;
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top->clk = 1;
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postReset();
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@ -226,6 +231,9 @@ public:
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try {
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// run simulation for 100 clock periods
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uint32_t iRsp_inst_next = top->iRsp_inst;
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uint32_t dRsp_inst_next = VL_RANDOM_I(32);
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bool iRsp_ready_pending = false, dRsp_ready_pending = false;
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for (i = 16; i < timeout*2; i+=2) {
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mTime = i/2;
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#ifdef CSR
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@ -233,12 +241,21 @@ public:
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//if(mTime == mTimeCmp) printf("SIM timer tick\n");
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#endif
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currentTime = i;
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uint32_t iRsp_inst_next = top->iRsp_inst;
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uint32_t dRsp_inst_next = VL_RANDOM_I(32);
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if (top->iCmd_valid && top->iCmd_ready) {
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// dump variables into VCD file and toggle clock
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dump(i);
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top->clk = 0;
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top->eval(); top->eval();top->eval();
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dump(i + 1);
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if (top->iCmd_valid && top->iCmd_ready && !iRsp_ready_pending) {
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assertEq(top->iCmd_payload_pc & 3,0);
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iRsp_ready_pending = true;
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//printf("%d\n",top->iCmd_payload_pc);
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iRsp_inst_next = iRspOverride((mem[top->iCmd_payload_pc + 0] << 0)
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@ -246,11 +263,12 @@ public:
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| (mem[top->iCmd_payload_pc + 2] << 16)
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| (mem[top->iCmd_payload_pc + 3] << 24));
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}
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if (top->dCmd_valid && top->dCmd_ready) {
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if (top->dCmd_valid && top->dCmd_ready && ! dRsp_ready_pending) {
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// assertEq(top->iCmd_payload_pc & 3,0);
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dRsp_ready_pending = true;
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dRsp_inst_next = VL_RANDOM_I(32);
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//printf("%d\n",top->iCmd_payload_pc);
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uint32_t addr = top->dCmd_payload_address;
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@ -307,34 +325,37 @@ public:
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}
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}
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// dump variables into VCD file and toggle clock
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for (uint32_t clk = 0; clk < 2; clk++) {
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dump(i+ clk);
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top->clk = !top->clk;
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top->eval();
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if(top->clk == 0){
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if(iStall) top->iCmd_ready = VL_RANDOM_I(1);
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if(dStall) top->dCmd_ready = VL_RANDOM_I(1);
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if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
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regTraces <<
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#ifdef TRACE_WITH_TIME
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currentTime <<
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#endif
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" : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
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}
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checks();
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}
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if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
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regTraces <<
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#ifdef TRACE_WITH_TIME
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currentTime <<
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#endif
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" : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
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}
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checks();
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top->clk = 1;
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top->eval(); top->eval();
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cycles += 1;
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top->iRsp_ready = !iRsp_ready_pending;
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top->dRsp_ready = 0;
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if(iRsp_ready_pending && (!iStall || VL_RANDOM_I(8) < 100)){
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top->iRsp_inst = iRsp_inst_next;
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iRsp_ready_pending = false;
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top->iRsp_ready = 1;
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}
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if(dRsp_ready_pending && (!dStall || VL_RANDOM_I(8) < 100)){
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top->dRsp_data = dRsp_inst_next;
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dRsp_ready_pending = false;
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top->dRsp_ready = 1;
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} else{
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top->dRsp_data = VL_RANDOM_I(32);
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}
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if(iStall) top->iCmd_ready = VL_RANDOM_I(8) < 100 && !iRsp_ready_pending;
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if(dStall) top->dCmd_ready = VL_RANDOM_I(8) < 100 && !dRsp_ready_pending;
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top->iRsp_inst = iRsp_inst_next;
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top->dRsp_data = dRsp_inst_next;
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if (Verilated::gotFinish())
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exit(0);
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@ -598,7 +619,7 @@ int main(int argc, char **argv, char **env) {
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#ifdef CSR
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uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
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8,6,9,6,10,4,11,4, 12,13,0, 14,2,15 };
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redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(2e3);)
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redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(4e3);)
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#endif
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#endif
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