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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings

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This commit is contained in:
Dolu1990 2018-03-14 00:56:23 +01:00
parent d9b7426cde
commit 63c1b738ff
3 changed files with 25 additions and 12 deletions
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16
README.md
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@ -348,16 +348,16 @@ There is some measurements of Murax SoC timings and area :
```
Murax interlocked stages (0.45 DMIPS/Mhz) ->
Artix 7 -> 304 Mhz 1016 LUT 1296 FF
Cyclone V -> 165 Mhz 736 ALMs
Cyclone IV -> 151 Mhz 1,463 LUT 1,254 FF
ICE40-HX -> 51 Mhz 2387 LC (icestorm)
Artix 7 -> 305 Mhz 1004 LUT 1297 FF
Cyclone V -> 160 Mhz 744 ALMs
Cyclone IV -> 148 Mhz 1,522 LUT 1,255 FF
ICE40-HX -> 51 Mhz 2402 LC (icestorm)
MuraxFast bypassed stages (0.65 DMIPS/Mhz) ->
Artix 7 -> 301 Mhz 1248 LUT 1393 FF
Cyclone V -> 163 Mhz 872 ALMs
Cyclone IV -> 145 Mhz 1,712 LUT 1,288 FF
ICE40-HX -> 45 Mhz, 2718 LC (icestorm)
Artix 7 -> 312 Mhz 1240 LUT 1330 FF
Cyclone V -> 159 Mhz 884 ALMs
Cyclone IV -> 142 Mhz 1,755 LUT 1,289 FF
ICE40-HX -> 50 Mhz, 2787 LC (icestorm)
```
There is some scripts to generate the SoC and call the icestorm toolchain there : scripts/Murax/

2
src/main/scala/vexriscv/demo/MuraxUtiles.scala
View file

@ -163,7 +163,7 @@ class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean
}
}
class MuraxSimpleBusDecoder(master : SimpleBus, specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
val masterPipelined = SimpleBus(master.config)
if(!pipelineMaster) {
masterPipelined.cmd << master.cmd

19
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
View file

@ -6,8 +6,19 @@ import spinal.lib._
import scala.collection.mutable.ArrayBuffer
object KeepAttribute{
object syn_keep extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
override def isLanguageReady(language: Language) : Boolean = language == Language.VERILOG || language == Language.SYSTEM_VERILOG
}
object keep extends AttributeFlag("keep")
def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep)
}
class PcManagerSimplePlugin(resetVector : BigInt,
relaxedPcCalculation : Boolean = false) extends Plugin[VexRiscv] with JumpService{
relaxedPcCalculation : Boolean = false,
keepPcPlus4 : Boolean = true) extends Plugin[VexRiscv] with JumpService{
//FetchService interface
case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int)
val jumpInfos = ArrayBuffer[JumpInfo]()
@ -17,7 +28,7 @@ class PcManagerSimplePlugin(resetVector : BigInt,
interface
}
var prefetchExceptionPort : Flow[ExceptionCause] = null
override def setup(pipeline: VexRiscv): Unit = {
if(!relaxedPcCalculation) pipeline.unremovableStages += pipeline.prefetch
}
@ -53,8 +64,10 @@ class PcManagerSimplePlugin(resetVector : BigInt,
//PC calculation without Jump
val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
val pcPlus4 = pcReg + 4
if(keepPcPlus4) KeepAttribute(pcPlus4)
when(arbitration.isFiring){
pcReg := pcReg + 4
pcReg := pcPlus4
}
//JumpService hardware implementation