mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-23 21:47:06 -04:00
Fix csrrs/csrrc for xip registers
This commit is contained in:
Dolu1990
parent
505bff6f45
commit
7159237104
5 changed files with 395 additions and 148 deletions
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@ -214,6 +214,7 @@ object CsrPluginConfig{
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}
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case class CsrWrite(that : Data, bitOffset : Int)
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case class CsrRead(that : Data , bitOffset : Int)
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case class CsrReadToWriteOverride(that : Data, bitOffset : Int) //Used for special cases, as MIP where there shadow stuff
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case class CsrOnWrite(doThat :() => Unit)
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case class CsrOnRead(doThat : () => Unit)
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case class CsrMapping() extends CsrInterface{
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@ -221,6 +222,7 @@ case class CsrMapping() extends CsrInterface{
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def addMappingAt(address : Int,that : Any) = mapping.getOrElseUpdate(address,new ArrayBuffer[Any]) += that
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override def r(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrRead(that,bitOffset))
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override def w(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrWrite(that,bitOffset))
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override def r2w(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrReadToWriteOverride(that,bitOffset))
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override def onWrite(csrAddress: Int)(body: => Unit): Unit = addMappingAt(csrAddress, CsrOnWrite(() => body))
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override def onRead(csrAddress: Int)(body: => Unit): Unit = addMappingAt(csrAddress, CsrOnRead(() => {body}))
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}
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@ -236,6 +238,8 @@ trait CsrInterface{
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w(csrAddress,bitOffset,that)
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}
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def r2w(csrAddress : Int, bitOffset : Int,that : Data): Unit
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def rw(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) rw(csrAddress,that._1, that._2)
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def w(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) w(csrAddress,that._1, that._2)
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def r(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) r(csrAddress,that._1, that._2)
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@ -324,6 +328,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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override def r(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.r(csrAddress, bitOffset, that)
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override def w(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.w(csrAddress, bitOffset, that)
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override def r2w(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.r2w(csrAddress, bitOffset, that)
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override def onWrite(csrAddress: Int)(body: => Unit): Unit = csrMapping.onWrite(csrAddress)(body)
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override def onRead(csrAddress: Int)(body: => Unit): Unit = csrMapping.onRead(csrAddress)(body)
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@ -531,7 +536,10 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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//Supervisor CSR
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for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) READ_WRITE(offset,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE)
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for(offset <- List(CSR.MIP, CSR.SIP)) {
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READ_WRITE(offset, 9 -> sip.SEIP_SOFT, 5 -> sip.STIP, 1 -> sip.SSIP)
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READ_WRITE(offset, 5 -> sip.STIP, 1 -> sip.SSIP)
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READ_ONLY(offset, 9 -> sip.SEIP_OR)
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WRITE_ONLY(offset, 9 -> sip.SEIP_SOFT)
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r2w(offset, 9, sip.SEIP_SOFT)
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}
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for(offset <- List(CSR.MIE, CSR.SIE)) READ_WRITE(offset, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE)
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@ -907,9 +915,11 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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// False -> writeSrc,
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// True -> Mux(input(INSTRUCTION)(12), ~writeSrc, writeSrc)
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// )
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val readToWriteData = CombInit(readData)
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val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
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False -> writeSrc,
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True -> Mux(input(INSTRUCTION)(12), readData & ~writeSrc, readData | writeSrc)
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True -> Mux(input(INSTRUCTION)(12), readToWriteData & ~writeSrc, readToWriteData | writeSrc)
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)
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@ -974,6 +984,17 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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}
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}
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switch(csrAddress) {
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for ((address, jobs) <- csrMapping.mapping if jobs.exists(_.isInstanceOf[CsrReadToWriteOverride])) {
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is(address) {
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for (element <- jobs) element match {
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case element: CsrReadToWriteOverride if element.that.getBitsWidth != 0 => readToWriteData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits
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case _ =>
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}
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}
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}
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}
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illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt)
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illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR))
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})
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@ -7,14 +7,14 @@ Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: 00100e93 li t4,1
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80000004: 00000097 auipc ra,0x0
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80000008: 50408093 addi ra,ra,1284 # 80000508 <mtrap>
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80000008: 68408093 addi ra,ra,1668 # 80000688 <mtrap>
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8000000c: 30509073 csrw mtvec,ra
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80000010: 00000097 auipc ra,0x0
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80000014: 52c08093 addi ra,ra,1324 # 8000053c <strap>
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80000014: 6ac08093 addi ra,ra,1708 # 800006bc <strap>
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80000018: 10509073 csrw stvec,ra
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8000001c: f00110b7 lui ra,0xf0011
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80000020: 00000113 li sp,0
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80000024: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000024: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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80000028 <test1>:
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80000028: 00100e13 li t3,1
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@ -33,18 +33,18 @@ Disassembly of section .crt_section:
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80000054: 01408093 addi ra,ra,20 # 80000064 <test2+0x2c>
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80000058: 34109073 csrw mepc,ra
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8000005c: 30200073 mret
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80000060: 4900006f j 800004f0 <fail>
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80000060: 6100006f j 80000670 <fail>
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80000064: 00000f17 auipc t5,0x0
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80000068: 024f0f13 addi t5,t5,36 # 80000088 <test4>
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8000006c: 00000073 ecall
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80000070: 4800006f j 800004f0 <fail>
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80000070: 6000006f j 80000670 <fail>
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80000074 <test3>:
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80000074: 00300e13 li t3,3
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80000078: 00000f17 auipc t5,0x0
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8000007c: 010f0f13 addi t5,t5,16 # 80000088 <test4>
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80000080: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000084: 46c0006f j 800004f0 <fail>
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80000084: 5ec0006f j 80000670 <fail>
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80000088 <test4>:
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80000088: 00400e13 li t3,4
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@ -58,11 +58,11 @@ Disassembly of section .crt_section:
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800000a8: 01408093 addi ra,ra,20 # 800000b8 <test4+0x30>
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800000ac: 34109073 csrw mepc,ra
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800000b0: 30200073 mret
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800000b4: 43c0006f j 800004f0 <fail>
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800000b4: 5bc0006f j 80000670 <fail>
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800000b8: 00000f17 auipc t5,0x0
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800000bc: 010f0f13 addi t5,t5,16 # 800000c8 <test5>
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800000c0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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800000c4: 42c0006f j 800004f0 <fail>
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800000c4: 5ac0006f j 80000670 <fail>
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800000c8 <test5>:
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800000c8: 00500e13 li t3,5
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@ -75,11 +75,11 @@ Disassembly of section .crt_section:
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800000e4: 01408093 addi ra,ra,20 # 800000f4 <test5+0x2c>
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800000e8: 34109073 csrw mepc,ra
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800000ec: 30200073 mret
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800000f0: 4000006f j 800004f0 <fail>
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800000f0: 5800006f j 80000670 <fail>
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800000f4: 00000f17 auipc t5,0x0
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800000f8: 010f0f13 addi t5,t5,16 # 80000104 <test6>
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800000fc: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000100: 3f00006f j 800004f0 <fail>
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80000100: 5700006f j 80000670 <fail>
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80000104 <test6>:
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80000104: 00600e13 li t3,6
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@ -91,7 +91,7 @@ Disassembly of section .crt_section:
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80000114: 00000f17 auipc t5,0x0
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80000118: 010f0f13 addi t5,t5,16 # 80000124 <test8>
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8000011c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000120: 3d00006f j 800004f0 <fail>
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80000120: 5500006f j 80000670 <fail>
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80000124 <test8>:
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80000124: 00800e13 li t3,8
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@ -107,9 +107,9 @@ Disassembly of section .crt_section:
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8000014c: 01408093 addi ra,ra,20 # 8000015c <test8+0x38>
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80000150: 34109073 csrw mepc,ra
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80000154: 30200073 mret
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80000158: 3980006f j 800004f0 <fail>
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80000158: 5180006f j 80000670 <fail>
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8000015c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000160: 3900006f j 800004f0 <fail>
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80000160: 5100006f j 80000670 <fail>
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80000164 <test9>:
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80000164: 00900e13 li t3,9
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@ -124,9 +124,9 @@ Disassembly of section .crt_section:
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80000188: 01408093 addi ra,ra,20 # 80000198 <test9+0x34>
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8000018c: 34109073 csrw mepc,ra
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80000190: 30200073 mret
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80000194: 35c0006f j 800004f0 <fail>
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80000194: 4dc0006f j 80000670 <fail>
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80000198: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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8000019c: 3540006f j 800004f0 <fail>
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8000019c: 4d40006f j 80000670 <fail>
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800001a0 <test10>:
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800001a0: 00a00e13 li t3,10
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@ -134,7 +134,7 @@ Disassembly of section .crt_section:
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800001a8: 03cf0f13 addi t5,t5,60 # 800001e0 <test11>
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800001ac: f00110b7 lui ra,0xf0011
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800001b0: 00000113 li sp,0
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800001b4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001b4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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800001b8: 00800093 li ra,8
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800001bc: 30009073 csrw mstatus,ra
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800001c0: 000010b7 lui ra,0x1
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@ -142,9 +142,9 @@ Disassembly of section .crt_section:
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800001c8: 30409073 csrw mie,ra
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800001cc: f00110b7 lui ra,0xf0011
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800001d0: 00100113 li sp,1
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800001d4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001d4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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800001d8: 10500073 wfi
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800001dc: 3140006f j 800004f0 <fail>
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800001dc: 4940006f j 80000670 <fail>
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800001e0 <test11>:
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800001e0: 00b00e13 li t3,11
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@ -152,7 +152,7 @@ Disassembly of section .crt_section:
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800001e8: 068f0f13 addi t5,t5,104 # 8000024c <test12>
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800001ec: f00110b7 lui ra,0xf0011
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800001f0: 00000113 li sp,0
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800001f4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001f4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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800001f8: 00800093 li ra,8
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800001fc: 30009073 csrw mstatus,ra
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80000200: 000010b7 lui ra,0x1
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@ -168,12 +168,12 @@ Disassembly of section .crt_section:
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80000228: 01408093 addi ra,ra,20 # 80000238 <test11+0x58>
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8000022c: 34109073 csrw mepc,ra
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80000230: 30200073 mret
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80000234: 2bc0006f j 800004f0 <fail>
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80000234: 43c0006f j 80000670 <fail>
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80000238: f00110b7 lui ra,0xf0011
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8000023c: 00100113 li sp,1
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80000240: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000240: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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80000244: 10500073 wfi
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80000248: 2a80006f j 800004f0 <fail>
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80000248: 4280006f j 80000670 <fail>
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8000024c <test12>:
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8000024c: 00c00e13 li t3,12
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@ -181,7 +181,7 @@ Disassembly of section .crt_section:
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80000254: 064f0f13 addi t5,t5,100 # 800002b4 <test14>
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80000258: f00110b7 lui ra,0xf0011
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8000025c: 00000113 li sp,0
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80000260: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000260: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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80000264: 00800093 li ra,8
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80000268: 30009073 csrw mstatus,ra
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8000026c: 000010b7 lui ra,0x1
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@ -196,12 +196,12 @@ Disassembly of section .crt_section:
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80000290: 01408093 addi ra,ra,20 # 800002a0 <test12+0x54>
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80000294: 34109073 csrw mepc,ra
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80000298: 30200073 mret
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8000029c: 2540006f j 800004f0 <fail>
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8000029c: 3d40006f j 80000670 <fail>
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800002a0: f00110b7 lui ra,0xf0011
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800002a4: 00100113 li sp,1
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800002a8: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800002a8: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010944>
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800002ac: 10500073 wfi
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800002b0: 2400006f j 800004f0 <fail>
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800002b0: 3c00006f j 80000670 <fail>
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800002b4 <test14>:
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800002b4: 00200093 li ra,2
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@ -211,7 +211,7 @@ Disassembly of section .crt_section:
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800002c4: 040f0f13 addi t5,t5,64 # 80000300 <test15>
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800002c8: f00120b7 lui ra,0xf0012
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800002cc: 00000113 li sp,0
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800002d0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800002d0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
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800002d4: 00200093 li ra,2
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800002d8: 30009073 csrw mstatus,ra
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800002dc: 20000093 li ra,512
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@ -219,7 +219,7 @@ Disassembly of section .crt_section:
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800002e4: 00000e93 li t4,0
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800002e8: f00120b7 lui ra,0xf0012
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800002ec: 00100113 li sp,1
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800002f0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800002f0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
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800002f4: 06400093 li ra,100
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800002f8: fff08093 addi ra,ra,-1
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800002fc: fe104ee3 bgtz ra,800002f8 <test14+0x44>
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@ -230,7 +230,7 @@ Disassembly of section .crt_section:
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80000308: 068f0f13 addi t5,t5,104 # 8000036c <test16>
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8000030c: f00120b7 lui ra,0xf0012
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80000310: 00000113 li sp,0
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80000314: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000314: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
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80000318: 00200093 li ra,2
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8000031c: 30009073 csrw mstatus,ra
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80000320: 20000093 li ra,512
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@ -245,13 +245,13 @@ Disassembly of section .crt_section:
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80000344: 01408093 addi ra,ra,20 # 80000354 <test15+0x54>
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80000348: 34109073 csrw mepc,ra
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8000034c: 30200073 mret
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80000350: 1a00006f j 800004f0 <fail>
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80000350: 3200006f j 80000670 <fail>
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80000354: 00100e93 li t4,1
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80000358: f00120b7 lui ra,0xf0012
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8000035c: 00100113 li sp,1
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80000360: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000360: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
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80000364: 10500073 wfi
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80000368: 1880006f j 800004f0 <fail>
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80000368: 3080006f j 80000670 <fail>
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8000036c <test16>:
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8000036c: 01000e13 li t3,16
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@ -259,7 +259,7 @@ Disassembly of section .crt_section:
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80000374: 060f0f13 addi t5,t5,96 # 800003d0 <test17>
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80000378: f00120b7 lui ra,0xf0012
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8000037c: 00000113 li sp,0
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80000380: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000380: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
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80000384: 00200093 li ra,2
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80000388: 30009073 csrw mstatus,ra
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8000038c: 20000093 li ra,512
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@ -273,12 +273,12 @@ Disassembly of section .crt_section:
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800003ac: 01408093 addi ra,ra,20 # 800003bc <test16+0x50>
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800003b0: 34109073 csrw mepc,ra
|
||||
800003b4: 30200073 mret
|
||||
800003b8: 1380006f j 800004f0 <fail>
|
||||
800003b8: 2b80006f j 80000670 <fail>
|
||||
800003bc: f00120b7 lui ra,0xf0012
|
||||
800003c0: 00100113 li sp,1
|
||||
800003c4: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
800003c4: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
800003c8: 10500073 wfi
|
||||
800003cc: 1240006f j 800004f0 <fail>
|
||||
800003cc: 2a40006f j 80000670 <fail>
|
||||
|
||||
800003d0 <test17>:
|
||||
800003d0: 01100e13 li t3,17
|
||||
|
|
@ -288,7 +288,7 @@ Disassembly of section .crt_section:
|
|||
800003e0: 040f0f13 addi t5,t5,64 # 8000041c <test18>
|
||||
800003e4: f00120b7 lui ra,0xf0012
|
||||
800003e8: 00000113 li sp,0
|
||||
800003ec: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
800003ec: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
800003f0: 00200093 li ra,2
|
||||
800003f4: 30009073 csrw mstatus,ra
|
||||
800003f8: 20000093 li ra,512
|
||||
|
|
@ -296,7 +296,7 @@ Disassembly of section .crt_section:
|
|||
80000400: 00000e93 li t4,0
|
||||
80000404: f00120b7 lui ra,0xf0012
|
||||
80000408: 00100113 li sp,1
|
||||
8000040c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
8000040c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000410: 06400093 li ra,100
|
||||
80000414: fff08093 addi ra,ra,-1
|
||||
80000418: fe104ee3 bgtz ra,80000414 <test17+0x44>
|
||||
|
|
@ -307,7 +307,7 @@ Disassembly of section .crt_section:
|
|||
80000424: 068f0f13 addi t5,t5,104 # 80000488 <test19>
|
||||
80000428: f00120b7 lui ra,0xf0012
|
||||
8000042c: 00000113 li sp,0
|
||||
80000430: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
80000430: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000434: 00200093 li ra,2
|
||||
80000438: 30009073 csrw mstatus,ra
|
||||
8000043c: 20000093 li ra,512
|
||||
|
|
@ -322,13 +322,13 @@ Disassembly of section .crt_section:
|
|||
80000460: 01408093 addi ra,ra,20 # 80000470 <test18+0x54>
|
||||
80000464: 34109073 csrw mepc,ra
|
||||
80000468: 30200073 mret
|
||||
8000046c: 0840006f j 800004f0 <fail>
|
||||
8000046c: 2040006f j 80000670 <fail>
|
||||
80000470: 00100e93 li t4,1
|
||||
80000474: f00120b7 lui ra,0xf0012
|
||||
80000478: 00100113 li sp,1
|
||||
8000047c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
8000047c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000480: 10500073 wfi
|
||||
80000484: 06c0006f j 800004f0 <fail>
|
||||
80000484: 1ec0006f j 80000670 <fail>
|
||||
|
||||
80000488 <test19>:
|
||||
80000488: 01300e13 li t3,19
|
||||
|
|
@ -336,7 +336,7 @@ Disassembly of section .crt_section:
|
|||
80000490: 060f0f13 addi t5,t5,96 # 800004ec <test20>
|
||||
80000494: f00120b7 lui ra,0xf0012
|
||||
80000498: 00000113 li sp,0
|
||||
8000049c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
8000049c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
800004a0: 00200093 li ra,2
|
||||
800004a4: 30009073 csrw mstatus,ra
|
||||
800004a8: 20000093 li ra,512
|
||||
|
|
@ -350,50 +350,152 @@ Disassembly of section .crt_section:
|
|||
800004c8: 01408093 addi ra,ra,20 # 800004d8 <test19+0x50>
|
||||
800004cc: 34109073 csrw mepc,ra
|
||||
800004d0: 30200073 mret
|
||||
800004d4: 01c0006f j 800004f0 <fail>
|
||||
800004d4: 19c0006f j 80000670 <fail>
|
||||
800004d8: f00120b7 lui ra,0xf0012
|
||||
800004dc: 00100113 li sp,1
|
||||
800004e0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
800004e0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
800004e4: 10500073 wfi
|
||||
800004e8: 0080006f j 800004f0 <fail>
|
||||
800004e8: 1880006f j 80000670 <fail>
|
||||
|
||||
800004ec <test20>:
|
||||
800004ec: 0100006f j 800004fc <pass>
|
||||
800004ec: f00120b7 lui ra,0xf0012
|
||||
800004f0: 00000113 li sp,0
|
||||
800004f4: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
800004f8: 01400e13 li t3,20
|
||||
800004fc: 00000f17 auipc t5,0x0
|
||||
80000500: 030f0f13 addi t5,t5,48 # 8000052c <test21>
|
||||
80000504: 00200093 li ra,2
|
||||
80000508: 30009073 csrw mstatus,ra
|
||||
8000050c: 20000093 li ra,512
|
||||
80000510: 30409073 csrw mie,ra
|
||||
80000514: 00000e93 li t4,0
|
||||
80000518: 20000093 li ra,512
|
||||
8000051c: 1440a073 csrs sip,ra
|
||||
80000520: 06400093 li ra,100
|
||||
80000524: fff08093 addi ra,ra,-1
|
||||
80000528: fe104ee3 bgtz ra,80000524 <test20+0x38>
|
||||
|
||||
800004f0 <fail>:
|
||||
800004f0: f0100137 lui sp,0xf0100
|
||||
800004f4: f2410113 addi sp,sp,-220 # f00fff24 <strap+0x700ff9e8>
|
||||
800004f8: 01c12023 sw t3,0(sp)
|
||||
8000052c <test21>:
|
||||
8000052c: 01500e13 li t3,21
|
||||
80000530: 00000f17 auipc t5,0x0
|
||||
80000534: 060f0f13 addi t5,t5,96 # 80000590 <test22>
|
||||
80000538: 20000093 li ra,512
|
||||
8000053c: 1440b073 csrc sip,ra
|
||||
80000540: 00200093 li ra,2
|
||||
80000544: 30009073 csrw mstatus,ra
|
||||
80000548: 20000093 li ra,512
|
||||
8000054c: 30409073 csrw mie,ra
|
||||
80000550: 000020b7 lui ra,0x2
|
||||
80000554: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
80000558: 00001137 lui sp,0x1
|
||||
8000055c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
|
||||
80000560: 3000b073 csrc mstatus,ra
|
||||
80000564: 30012073 csrs mstatus,sp
|
||||
80000568: 00000097 auipc ra,0x0
|
||||
8000056c: 01408093 addi ra,ra,20 # 8000057c <test21+0x50>
|
||||
80000570: 34109073 csrw mepc,ra
|
||||
80000574: 30200073 mret
|
||||
80000578: 0f80006f j 80000670 <fail>
|
||||
8000057c: 00100e93 li t4,1
|
||||
80000580: 20000093 li ra,512
|
||||
80000584: 1440a073 csrs sip,ra
|
||||
80000588: 10500073 wfi
|
||||
8000058c: 0e40006f j 80000670 <fail>
|
||||
|
||||
800004fc <pass>:
|
||||
800004fc: f0100137 lui sp,0xf0100
|
||||
80000500: f2010113 addi sp,sp,-224 # f00fff20 <strap+0x700ff9e4>
|
||||
80000504: 00012023 sw zero,0(sp)
|
||||
80000590 <test22>:
|
||||
80000590: 01600e13 li t3,22
|
||||
80000594: 00000f17 auipc t5,0x0
|
||||
80000598: 058f0f13 addi t5,t5,88 # 800005ec <test23>
|
||||
8000059c: 20000093 li ra,512
|
||||
800005a0: 1440b073 csrc sip,ra
|
||||
800005a4: 00200093 li ra,2
|
||||
800005a8: 30009073 csrw mstatus,ra
|
||||
800005ac: 20000093 li ra,512
|
||||
800005b0: 30409073 csrw mie,ra
|
||||
800005b4: 20000093 li ra,512
|
||||
800005b8: 1440a073 csrs sip,ra
|
||||
800005bc: 000020b7 lui ra,0x2
|
||||
800005c0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
800005c4: 00000113 li sp,0
|
||||
800005c8: 3000b073 csrc mstatus,ra
|
||||
800005cc: 30012073 csrs mstatus,sp
|
||||
800005d0: 00000097 auipc ra,0x0
|
||||
800005d4: 01408093 addi ra,ra,20 # 800005e4 <test22+0x54>
|
||||
800005d8: 34109073 csrw mepc,ra
|
||||
800005dc: 30200073 mret
|
||||
800005e0: 0900006f j 80000670 <fail>
|
||||
800005e4: 10500073 wfi
|
||||
800005e8: 0880006f j 80000670 <fail>
|
||||
|
||||
80000508 <mtrap>:
|
||||
80000508: fe0e84e3 beqz t4,800004f0 <fail>
|
||||
8000050c: 342020f3 csrr ra,mcause
|
||||
80000510: 341020f3 csrr ra,mepc
|
||||
80000514: 300020f3 csrr ra,mstatus
|
||||
80000518: 08000093 li ra,128
|
||||
8000051c: 3000b073 csrc mstatus,ra
|
||||
80000520: 00200093 li ra,2
|
||||
80000524: fc1e8ce3 beq t4,ra,800004fc <pass>
|
||||
80000528: 000020b7 lui ra,0x2
|
||||
8000052c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
80000530: 3000a073 csrs mstatus,ra
|
||||
80000534: 341f1073 csrw mepc,t5
|
||||
80000538: 30200073 mret
|
||||
800005ec <test23>:
|
||||
800005ec: 01700e13 li t3,23
|
||||
800005f0: 00000e93 li t4,0
|
||||
800005f4: f00120b7 lui ra,0xf0012
|
||||
800005f8: 00000113 li sp,0
|
||||
800005fc: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000600: 20000093 li ra,512
|
||||
80000604: 1440b073 csrc sip,ra
|
||||
80000608: 344021f3 csrr gp,mip
|
||||
8000060c: f00120b7 lui ra,0xf0012
|
||||
80000610: 00100113 li sp,1
|
||||
80000614: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000618: 20000093 li ra,512
|
||||
8000061c: 1440b073 csrc sip,ra
|
||||
80000620: 344021f3 csrr gp,mip
|
||||
80000624: f00120b7 lui ra,0xf0012
|
||||
80000628: 00000113 li sp,0
|
||||
8000062c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000630: 20000093 li ra,512
|
||||
80000634: 1440b073 csrc sip,ra
|
||||
80000638: 344021f3 csrr gp,mip
|
||||
8000063c: f00120b7 lui ra,0xf0012
|
||||
80000640: 00000113 li sp,0
|
||||
80000644: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000648: 20000093 li ra,512
|
||||
8000064c: 1440a073 csrs sip,ra
|
||||
80000650: 344021f3 csrr gp,mip
|
||||
80000654: f00120b7 lui ra,0xf0012
|
||||
80000658: 00100113 li sp,1
|
||||
8000065c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011944>
|
||||
80000660: 20000093 li ra,512
|
||||
80000664: 1440a073 csrs sip,ra
|
||||
80000668: 344021f3 csrr gp,mip
|
||||
8000066c: 0100006f j 8000067c <pass>
|
||||
|
||||
8000053c <strap>:
|
||||
8000053c: fa0e8ae3 beqz t4,800004f0 <fail>
|
||||
80000540: 142020f3 csrr ra,scause
|
||||
80000544: 141020f3 csrr ra,sepc
|
||||
80000548: 100020f3 csrr ra,sstatus
|
||||
8000054c: 00000073 ecall
|
||||
80000550: 00000013 nop
|
||||
80000554: 00000013 nop
|
||||
80000558: 00000013 nop
|
||||
8000055c: 00000013 nop
|
||||
80000560: 00000013 nop
|
||||
80000564: 00000013 nop
|
||||
80000670 <fail>:
|
||||
80000670: f0100137 lui sp,0xf0100
|
||||
80000674: f2410113 addi sp,sp,-220 # f00fff24 <strap+0x700ff868>
|
||||
80000678: 01c12023 sw t3,0(sp)
|
||||
|
||||
8000067c <pass>:
|
||||
8000067c: f0100137 lui sp,0xf0100
|
||||
80000680: f2010113 addi sp,sp,-224 # f00fff20 <strap+0x700ff864>
|
||||
80000684: 00012023 sw zero,0(sp)
|
||||
|
||||
80000688 <mtrap>:
|
||||
80000688: fe0e84e3 beqz t4,80000670 <fail>
|
||||
8000068c: 342020f3 csrr ra,mcause
|
||||
80000690: 341020f3 csrr ra,mepc
|
||||
80000694: 300020f3 csrr ra,mstatus
|
||||
80000698: 08000093 li ra,128
|
||||
8000069c: 3000b073 csrc mstatus,ra
|
||||
800006a0: 00200093 li ra,2
|
||||
800006a4: fc1e8ce3 beq t4,ra,8000067c <pass>
|
||||
800006a8: 000020b7 lui ra,0x2
|
||||
800006ac: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
800006b0: 3000a073 csrs mstatus,ra
|
||||
800006b4: 341f1073 csrw mepc,t5
|
||||
800006b8: 30200073 mret
|
||||
|
||||
800006bc <strap>:
|
||||
800006bc: fa0e8ae3 beqz t4,80000670 <fail>
|
||||
800006c0: 142020f3 csrr ra,scause
|
||||
800006c4: 141020f3 csrr ra,sepc
|
||||
800006c8: 100020f3 csrr ra,sstatus
|
||||
800006cc: 00000073 ecall
|
||||
800006d0: 00000013 nop
|
||||
800006d4: 00000013 nop
|
||||
800006d8: 00000013 nop
|
||||
800006dc: 00000013 nop
|
||||
800006e0: 00000013 nop
|
||||
800006e4: 00000013 nop
|
||||
|
|
|
|||
|
|
@ -1,48 +1,48 @@
|
|||
:0200000480007A
|
||||
:10000000930E100097000000938040507390503082
|
||||
:10001000970000009380C05273905010B71001F009
|
||||
:10000000930E10009700000093804068739050306A
|
||||
:10001000970000009380C06A73905010B71001F0F1
|
||||
:100020001301000023A02000130E1000170F000082
|
||||
:10003000130FCF0073000000130E2000B720000044
|
||||
:10004000938000801301000073B0003073200130F2
|
||||
:1000500097000000938040017390103473002030AB
|
||||
:100060006F000049170F0000130F4F0273000000CC
|
||||
:100070006F000048130E3000170F0000130F0F0120
|
||||
:10008000832010006F00C046130E4000B720000010
|
||||
:100060006F000061170F0000130F4F0273000000B4
|
||||
:100070006F000060130E3000170F0000130F0F0108
|
||||
:10008000832010006F00C05E130E4000B7200000F8
|
||||
:1000900093800080371100001301018073B000309D
|
||||
:1000A000732001309700000093804001739010345A
|
||||
:1000B000730020306F00C043170F0000130F0F01B3
|
||||
:1000C000832010006F00C042130E5000B7200000C4
|
||||
:1000B000730020306F00C05B170F0000130F0F019B
|
||||
:1000C000832010006F00C05A130E5000B7200000AC
|
||||
:1000D000938000801301000073B000307320013062
|
||||
:1000E000970000009380400173901034730020301B
|
||||
:1000F0006F000040170F0000130F0F018320100046
|
||||
:100100006F00003F130E60009300000173902030D9
|
||||
:1000F0006F000058170F0000130F0F01832010002E
|
||||
:100100006F000057130E60009300000173902030C1
|
||||
:10011000130E7000170F0000130F0F018320100043
|
||||
:100120006F00003D130E8000170F0000130FCF0368
|
||||
:100120006F000055130E8000170F0000130FCF0350
|
||||
:10013000B720000093800080371100001301018078
|
||||
:1001400073B00030732001309700000093804001AD
|
||||
:1001500073901034730020306F00803983201000BA
|
||||
:100160006F000039130E9000170F0000130F8F035C
|
||||
:1001500073901034730020306F00805183201000A2
|
||||
:100160006F000051130E9000170F0000130F8F0344
|
||||
:10017000B7200000938000801301000073B00030AE
|
||||
:100180007320013097000000938040017390103479
|
||||
:10019000730020306F00C035832010006F004035A1
|
||||
:10019000730020306F00C04D832010006F00404D71
|
||||
:1001A000130EA000170F0000130FCF03B71001F0BC
|
||||
:1001B0001301000023A02000930080007390003002
|
||||
:1001C000B71000009380008073904030B71001F0AA
|
||||
:1001D0001301100023A02000730050106F00403165
|
||||
:1001D0001301100023A02000730050106F0040494D
|
||||
:1001E000130EB000170F0000130F8F06B71001F0A9
|
||||
:1001F0001301000023A020009300800073900030C2
|
||||
:10020000B71000009380008073904030B72000004A
|
||||
:1002100093800080371100001301018073B000301B
|
||||
:1002200073200130970000009380400173901034D8
|
||||
:10023000730020306F00C02BB71001F013011000C5
|
||||
:1002400023A02000730050106F00802A130EC000FE
|
||||
:10023000730020306F00C043B71001F013011000AD
|
||||
:1002400023A02000730050106F008042130EC000E6
|
||||
:10025000170F0000130F4F06B71001F01301000035
|
||||
:1002600023A020009300800073900030B71000009E
|
||||
:100270009380008073904030B7200000938000800E
|
||||
:100280001301000073B000307320013097000000AC
|
||||
:100290009380400173901034730020306F0040252C
|
||||
:100290009380400173901034730020306F00403D14
|
||||
:1002A000B71001F01301100023A0200073005010BC
|
||||
:1002B0006F0000249300200073900010130EE000E4
|
||||
:1002B0006F00003C9300200073900010130EE000CC
|
||||
:1002C000170F0000130F0F04B72001F013010000F7
|
||||
:1002D00023A02000930020007390003093000020A2
|
||||
:1002E00073904030930E0000B72001F0130110000E
|
||||
|
|
@ -52,14 +52,14 @@
|
|||
:100320009300002073904030B7200000938000803D
|
||||
:10033000371100001301018073B0003073200130C9
|
||||
:1003400097000000938040017390103473002030B8
|
||||
:100350006F00001A930E1000B72001F01301100077
|
||||
:1003600023A02000730050106F008018130E0001AE
|
||||
:100350006F000032930E1000B72001F0130110005F
|
||||
:1003600023A02000730050106F008030130E000196
|
||||
:10037000170F0000130F0F06B72001F01301000044
|
||||
:1003800023A02000930020007390003093000020F1
|
||||
:1003900073904030B720000093800080130100006C
|
||||
:1003A00073B000307320013097000000938040014B
|
||||
:1003B00073901034730020306F008013B72001F069
|
||||
:1003C0001301100023A02000730050106F00401292
|
||||
:1003B00073901034730020306F00802BB72001F051
|
||||
:1003C0001301100023A02000730050106F00402A7A
|
||||
:1003D000130E10019300002073903030170F0000AF
|
||||
:1003E000130F0F04B72001F01301000023A0200019
|
||||
:1003F00093002000739000309300002073904030F1
|
||||
|
|
@ -69,22 +69,46 @@
|
|||
:1004300023A0200093002000739000309300002040
|
||||
:1004400073904030B7200000938000803711000087
|
||||
:100450001301018073B00030732001309700000059
|
||||
:100460009380400173901034730020306F00400877
|
||||
:100460009380400173901034730020306F0040205F
|
||||
:10047000930E1000B72001F01301100023A02000FC
|
||||
:10048000730050106F00C006130E3001170F0000EC
|
||||
:10048000730050106F00C01E130E3001170F0000D4
|
||||
:10049000130F0F06B72001F01301000023A0200066
|
||||
:1004A0009300200073900030930000207390403040
|
||||
:1004B000B7200000938000801301000073B000306B
|
||||
:1004C0007320013097000000938040017390103436
|
||||
:1004D000730020306F00C001B72001F0130110003D
|
||||
:1004E00023A02000730050106F0080006F000001F7
|
||||
:1004F000370110F0130141F22320C101370110F040
|
||||
:10050000130101F223200100E3840EFEF3202034C6
|
||||
:10051000F3201034F32000309300000873B0003053
|
||||
:1005200093002000E38C1EFCB72000009380008025
|
||||
:1005300073A0003073101F3473002030E38A0EFA6A
|
||||
:10054000F3202014F3201014F32000107300000097
|
||||
:10055000130000001300000013000000130000004F
|
||||
:0805600013000000130000006D
|
||||
:1004D000730020306F00C019B72001F01301100025
|
||||
:1004E00023A02000730050106F008018B72001F087
|
||||
:1004F0001301000023A02000130E4001170F00007D
|
||||
:10050000130F0F039300200073900030930000201E
|
||||
:1005100073904030930E00009300002073A04014AD
|
||||
:10052000930040069380F0FFE34E10FE130E50013F
|
||||
:10053000170F0000130F0F069300002073B0401434
|
||||
:10054000930020007390003093000020739040309F
|
||||
:10055000B720000093800080371100001301018054
|
||||
:1005600073B0003073200130970000009380400189
|
||||
:1005700073901034730020306F00800F930E1000C2
|
||||
:100580009300002073A04014730050106F00400EC1
|
||||
:10059000130E6001170F0000130F8F05930000204A
|
||||
:1005A00073B040149300200073900030930000203B
|
||||
:1005B000739040309300002073A04014B7200000D7
|
||||
:1005C000938000801301000073B00030732001306D
|
||||
:1005D0009700000093804001739010347300203026
|
||||
:1005E0006F000009730050106F008008130E700137
|
||||
:1005F000930E0000B72001F01301000023A020009B
|
||||
:100600009300002073B04014F3214034B72001F070
|
||||
:100610001301100023A020009300002073B04014A9
|
||||
:10062000F3214034B72001F01301000023A0200083
|
||||
:100630009300002073B04014F3214034B72001F040
|
||||
:100640001301000023A020009300002073A0401499
|
||||
:10065000F3214034B72001F01301100023A0200043
|
||||
:100660009300002073A04014F32140346F00000178
|
||||
:10067000370110F0130141F22320C101370110F0BE
|
||||
:10068000130101F223200100E3840EFEF320203445
|
||||
:10069000F3201034F32000309300000873B00030D2
|
||||
:1006A00093002000E38C1EFCB720000093800080A4
|
||||
:1006B00073A0003073101F3473002030E38A0EFAE9
|
||||
:1006C000F3202014F3201014F32000107300000016
|
||||
:1006D00013000000130000001300000013000000CE
|
||||
:0806E0001300000013000000EC
|
||||
:040000058000000077
|
||||
:00000001FF
|
||||
|
|
|
|||
|
|
@ -229,7 +229,89 @@ test19: //U external interrupt S with deleg
|
|||
j fail
|
||||
|
||||
|
||||
test20:
|
||||
|
||||
|
||||
|
||||
test20:// M external interrupt S by software with deleg
|
||||
externalInterruptS(0)
|
||||
li TEST_ID, 20
|
||||
la TRAP_RET, test21
|
||||
li x1, MSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
li TRAP_OK, 0
|
||||
li x1, 1 << 9
|
||||
csrs sip, x1
|
||||
delay()
|
||||
|
||||
test21: //S external interrupt S by software with deleg
|
||||
li TEST_ID, 21
|
||||
la TRAP_RET, test22
|
||||
li x1, 1 << 9
|
||||
csrc sip, x1
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
setPriv(1)
|
||||
li TRAP_OK, 1
|
||||
li x1, 1 << 9
|
||||
csrs sip, x1
|
||||
wfi
|
||||
j fail
|
||||
|
||||
test22: //U external interrupt S by software with deleg
|
||||
li TEST_ID, 22
|
||||
la TRAP_RET, test23
|
||||
li x1, 1 << 9
|
||||
csrc sip, x1
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
li x1, 1 << 9
|
||||
csrs sip, x1
|
||||
setPriv(0)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
|
||||
|
||||
test23: //Test software and hardware setting inettrupt
|
||||
li TEST_ID, 23
|
||||
li TRAP_OK, 0
|
||||
externalInterruptS(0)
|
||||
li x1, 1 << 9
|
||||
csrc sip, x1
|
||||
csrr x3, mip
|
||||
|
||||
|
||||
externalInterruptS(1)
|
||||
li x1, 1 << 9
|
||||
csrc sip, x1
|
||||
csrr x3, mip
|
||||
|
||||
|
||||
externalInterruptS(0)
|
||||
li x1, 1 << 9
|
||||
csrc sip, x1
|
||||
csrr x3, mip
|
||||
|
||||
|
||||
externalInterruptS(0)
|
||||
li x1, 1 << 9
|
||||
csrs sip, x1
|
||||
csrr x3, mip
|
||||
|
||||
|
||||
externalInterruptS(1)
|
||||
li x1, 1 << 9
|
||||
csrs sip, x1
|
||||
csrr x3, mip
|
||||
|
||||
|
||||
|
||||
j pass
|
||||
|
||||
fail:
|
||||
|
|
|
|||
|
|
@ -221,7 +221,6 @@ public:
|
|||
uint32_t medeleg;
|
||||
uint32_t mideleg;
|
||||
|
||||
uint32_t interrupts;
|
||||
|
||||
union status {
|
||||
uint32_t raw;
|
||||
|
|
@ -244,7 +243,10 @@ public:
|
|||
}__attribute__((packed)) status;
|
||||
|
||||
|
||||
union mip {
|
||||
|
||||
uint32_t ipInput;
|
||||
uint32_t ipSoft;
|
||||
union IpOr {
|
||||
uint32_t raw;
|
||||
struct {
|
||||
uint32_t _1a : 1;
|
||||
|
|
@ -260,8 +262,13 @@ public:
|
|||
uint32_t _3b : 1;
|
||||
uint32_t meip : 1;
|
||||
};
|
||||
}__attribute__((packed)) ip;
|
||||
}__attribute__((packed));
|
||||
|
||||
IpOr getIp(){
|
||||
IpOr ret;
|
||||
ret.raw = ipSoft | ipInput;
|
||||
return ret;
|
||||
}
|
||||
|
||||
union mie {
|
||||
uint32_t raw;
|
||||
|
|
@ -346,7 +353,6 @@ public:
|
|||
regs[i] = 0;
|
||||
|
||||
status.raw = 0;
|
||||
ip.raw = 0;
|
||||
ie.raw = 0;
|
||||
mtvec.raw = 0x80000020;
|
||||
mcause.raw = 0;
|
||||
|
|
@ -360,7 +366,8 @@ public:
|
|||
medeleg = 0;
|
||||
mideleg = 0;
|
||||
satp.mode = 0;
|
||||
interrupts = 0;
|
||||
ipSoft = 0;
|
||||
ipInput = 0;
|
||||
}
|
||||
|
||||
virtual void rfWrite(int32_t address, int32_t data) {
|
||||
|
|
@ -479,7 +486,7 @@ public:
|
|||
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||
switch(csr){
|
||||
case MSTATUS: *value = status.raw; break;
|
||||
case MIP: *value = ip.raw; break;
|
||||
case MIP: *value = getIp().raw; break;
|
||||
case MIE: *value = ie.raw; break;
|
||||
case MTVEC: *value = mtvec.raw; break;
|
||||
case MCAUSE: *value = mcause.raw; break;
|
||||
|
|
@ -491,7 +498,7 @@ public:
|
|||
case MIDELEG: *value = mideleg; break;
|
||||
|
||||
case SSTATUS: *value = status.raw & 0xC0133; break;
|
||||
case SIP: *value = ip.raw & 0x333; break;
|
||||
case SIP: *value = getIp().raw & 0x333; break;
|
||||
case SIE: *value = ie.raw & 0x333; break;
|
||||
case STVEC: *value = stvec.raw; break;
|
||||
case SCAUSE: *value = scause.raw; break;
|
||||
|
|
@ -504,12 +511,21 @@ public:
|
|||
return false;
|
||||
}
|
||||
|
||||
virtual uint32_t csrReadToWriteOverride(int32_t csr, uint32_t value){
|
||||
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||
switch(csr){
|
||||
case MIP: return ipSoft; break;
|
||||
case SIP: return ipSoft & 0x333; break;
|
||||
};
|
||||
return value;
|
||||
}
|
||||
|
||||
#define maskedWrite(dst, src, mask) dst=(dst & ~mask)|(src & mask);
|
||||
virtual bool csrWrite(int32_t csr, uint32_t value){
|
||||
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||
switch(csr){
|
||||
case MSTATUS: status.raw = value; break;
|
||||
case MIP: ip.raw = value; break;
|
||||
case MIP: ipSoft = value; break;
|
||||
case MIE: ie.raw = value; break;
|
||||
case MTVEC: mtvec.raw = value; break;
|
||||
case MCAUSE: mcause.raw = value; break;
|
||||
|
|
@ -521,7 +537,7 @@ public:
|
|||
case MIDELEG: mideleg = value; break;
|
||||
|
||||
case SSTATUS: maskedWrite(status.raw, value,0xC0133); break;
|
||||
case SIP: maskedWrite(ip.raw, value,0x333); break;
|
||||
case SIP: maskedWrite(ipSoft, value,0x333); break;
|
||||
case SIE: maskedWrite(ie.raw, value,0x333); break;
|
||||
case STVEC: stvec.raw = value; break;
|
||||
case SCAUSE: scause.raw = value; break;
|
||||
|
|
@ -563,9 +579,9 @@ public:
|
|||
uint32_t mEnabled = status.mie && privilege == 3 || privilege < 3;
|
||||
uint32_t sEnabled = status.sie && privilege == 1 || privilege < 1;
|
||||
|
||||
uint32_t masked = interrupts & ~mideleg & -mEnabled & ie.raw;
|
||||
uint32_t masked = getIp().raw & ~mideleg & -mEnabled & ie.raw;
|
||||
if (masked == 0)
|
||||
masked = interrupts & mideleg & -sEnabled & ie.raw & 0x333;
|
||||
masked = getIp().raw & mideleg & -sEnabled & ie.raw & 0x333;
|
||||
|
||||
if (masked) {
|
||||
if (masked & (MIP_MEIP | MIP_SEIP))
|
||||
|
|
@ -803,7 +819,7 @@ public:
|
|||
uint32_t csrAddress = i32_csr;
|
||||
uint32_t old;
|
||||
if(csrRead(i32_csr, &old)) { ilegalInstruction();return; }
|
||||
if(write) if(csrWrite(i32_csr, (old & ~clear) | set)) { ilegalInstruction();return; }
|
||||
if(write) if(csrWrite(i32_csr, (csrReadToWriteOverride(i32_csr, old) & ~clear) | set)) { ilegalInstruction();return; }
|
||||
rfWrite(rd32, old);
|
||||
pcWrite(pc + 4);
|
||||
}
|
||||
|
|
@ -1360,25 +1376,27 @@ public:
|
|||
top->eval();
|
||||
|
||||
#ifdef CSR
|
||||
riscvRef.interrupts = 0;
|
||||
#ifdef TIMER_INTERRUPT
|
||||
riscvRef.interrupts |= top->timerInterrupt << 7;
|
||||
#endif
|
||||
#ifdef EXTERNAL_INTERRUPT
|
||||
riscvRef.interrupts |= top->externalInterrupt << 11;
|
||||
#endif
|
||||
#ifdef CSR
|
||||
riscvRef.interrupts |= top->softwareInterrupt << 3;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
// riscvRef.interrupts |= top->timerInterruptS << 5;
|
||||
riscvRef.interrupts |= top->externalInterruptS << 9;
|
||||
#endif
|
||||
if(riscvRefEnable) {
|
||||
riscvRef.ipInput = 0;
|
||||
#ifdef TIMER_INTERRUPT
|
||||
riscvRef.ipInput |= top->timerInterrupt << 7;
|
||||
#endif
|
||||
#ifdef EXTERNAL_INTERRUPT
|
||||
riscvRef.ipInput |= top->externalInterrupt << 11;
|
||||
#endif
|
||||
#ifdef CSR
|
||||
riscvRef.ipInput |= top->softwareInterrupt << 3;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
// riscvRef.ipInput |= top->timerInterruptS << 5;
|
||||
riscvRef.ipInput |= top->externalInterruptS << 9;
|
||||
#endif
|
||||
|
||||
riscvRef.liveness(top->VexRiscv->execute_CsrPlugin_inWfi);
|
||||
if(top->VexRiscv->CsrPlugin_interruptJump){
|
||||
if(riscvRefEnable) riscvRef.trap(true, top->VexRiscv->CsrPlugin_interruptCode);
|
||||
}
|
||||
riscvRef.liveness(top->VexRiscv->execute_CsrPlugin_inWfi);
|
||||
if(top->VexRiscv->CsrPlugin_interruptJump){
|
||||
if(riscvRefEnable) riscvRef.trap(true, top->VexRiscv->CsrPlugin_interruptCode);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
if(top->VexRiscv->writeBack_arbitration_isFiring){
|
||||
if(riscvRefEnable) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue