Update bench config with realistic embedded CSR

README.md

@@ -3,7 +3,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
 - RV32IM instruction set
 - Interrupts and exception handling with the Machine mode from the riscv-privileged-v1.9.1 specification.
 - Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
-- 1.17 DMIPS/Mhz when all features are enabled extension
+- 1.16 DMIPS/Mhz when all features are enabled extension
 - Optimized for FPGA
 - Optional MUL/DIV/REM extension
 - Optional instruction and data caches
@@ -25,29 +25,29 @@ The following number where obtains by synthesis the CPU as toplevel without any
 The used CPU corresponding configuration can be find in src/scala/VexRiscv/demo.
 
 ```
-VexRiscv smallest no CSR ->
+VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
   Artix 7    -> 324 Mhz 478 LUT 539 FF 
   Cyclone V  -> 187 Mhz 341 ALMs
   Cyclone IV -> 180 Mhz 736 LUT 529 FF 
   Cyclone II -> 156 Mhz 740 LUT 528 FF 
   
-VexRiscv smallest ->
+VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass) ->
   Artix 7    -> 335 Mhz 560 LUT 589 FF 
   Cyclone V  -> 182 Mhz 420 ALMs
   Cyclone IV -> 160 Mhz 852 LUT 579 FF 
   Cyclone II -> 144 Mhz 844 LUT 578 FF 
   
-VexRiscv full no MMU ->
-  Artix 7    -> 227 Mhz 2280 LUT 1728 FF 
-  Cyclone V  -> 120 Mhz 1,540 ALMs
-  Cyclone IV -> 120 Mhz 3,282 LUT 1,987 FF 
-  Cyclone II -> 101 Mhz 3,347 LUT 1,986 FF 
-  
-VexRiscv full ->
-  Artix 7    -> 210 Mhz 2542 LUT 2246 FF 
-  Cyclone V  -> 114 Mhz 1,815 ALMs
-  Cyclone IV -> 96 Mhz 3,717 LUT 2,505 FF 
-  Cyclone II -> 94 Mhz 3,772 LUT 2,506 FF 
+VexRiscv full (RV32IM, 1.14 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
+  Artix 7    -> 249 Mhz 1862 LUT 1498 FF 
+  Cyclone V  -> 133 Mhz 1,272 ALMs
+  Cyclone IV -> 116 Mhz 2,727 LUT 1,759 FF 
+  Cyclone II -> 105 Mhz 2,771 LUT 1,758 FF 
+    
+VexRiscv full with MMU (RV32IM, 1.16 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch, MMU) ->
+  Artix 7    -> 210 Mhz 2104 LUT 2017 FF 
+  Cyclone V  -> 115 Mhz 1,503 ALMs
+  Cyclone IV -> 100 Mhz 3,145 LUT 2,278 FF 
+  Cyclone II -> 92 Mhz 3,195 LUT 2,279 FF 
 ```
 
 ## Dependencies

src/main/scala/VexRiscv/demo/GenFull.scala

@@ -79,7 +79,7 @@ object GenFull extends App{
         ),
         new MulPlugin,
         new DivPlugin,
-        new CsrPlugin(CsrPluginConfig.all),
+        new CsrPlugin(CsrPluginConfig.small),
         new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
         new BranchPlugin(
           earlyBranch = false,

src/main/scala/VexRiscv/demo/GenFullNoMmu.scala

@@ -70,7 +70,7 @@ object GenFullNoMmu extends App{
         ),
         new MulPlugin,
         new DivPlugin,
-        new CsrPlugin(CsrPluginConfig.all),
+        new CsrPlugin(CsrPluginConfig.small),
         new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
         new BranchPlugin(
           earlyBranch = false,