mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-24 05:57:07 -04:00
MachineCsr wireing/logic done
This commit is contained in:
Charles Papon
parent
de4c2470c8
commit
ed0660237f
2 changed files with 60 additions and 35 deletions
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@ -20,7 +20,7 @@ object CsrAccess {
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object NONE extends CsrAccess
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}
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case class ExceptionPortInfo(port : Flow[UInt],stage : Stage)
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage)
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case class MachineCsrConfig(
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mvendorid : BigInt,
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marchid : BigInt,
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@ -59,21 +59,26 @@ case class CsrMapping(){
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class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with ExceptionService {
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import config._
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import CsrAccess._
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def xlen = 32
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//Mannage ExceptionService calls
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val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
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def exceptionCodeWidth = 4
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override def newExceptionPort(stage : Stage) = {
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val interface = Flow(UInt(exceptionCodeWidth bits))
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val interface = Flow(ExceptionCause())
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exceptionPortsInfos += ExceptionPortInfo(interface,stage)
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interface
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}
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var jumpInterface : Flow[UInt] = null
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var pluginExceptionPort : Flow[UInt] = null
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var pluginExceptionPort : Flow[ExceptionCause] = null
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var timerInterrupt : Bool = null
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var externalInterrupt : Bool = null
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object EnvCtrlEnum extends SpinalEnum(binarySequential){
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val NONE, EBREAK, ECALL, MRET = newElement()
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@ -82,6 +87,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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object ENV_CTRL extends Stageable(EnvCtrlEnum())
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object EXCEPTION extends Stageable(Bool)
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object IS_CSR extends Stageable(Bool)
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object EXCEPTION_CAUSE extends Stageable(ExceptionCause())
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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@ -130,18 +136,16 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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pluginExceptionPort = newExceptionPort(pipeline.execute)
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pluginExceptionPort.valid := False
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pluginExceptionPort.payload.assignDontCare()
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timerInterrupt = in Bool()
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externalInterrupt = in Bool()
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}
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def xlen = 32
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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//Manage ECALL instructions
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when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){
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pluginExceptionPort.valid := True
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pluginExceptionPort.payload := 3
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}
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pipeline plug new Area{
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//Define CSR mapping utilities
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@ -158,7 +162,6 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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}
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//Define CSR registers
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val mtvec = RegInit(U(mtvecInit,xlen bits))
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val mepc = Reg(UInt(xlen bits))
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@ -166,7 +169,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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val MIE, MPIE = RegInit(False)
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}
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val mip = new Area{
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val MEIP, MTIP, MSIP = False //TODO
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val MEIP = RegNext(externalInterrupt) init(False)
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val MTIP = RegNext(timerInterrupt) init(False)
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val MSIP = RegInit(False)
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}
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val mie = new Area{
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val MEIE, MTIE, MSIE = RegInit(False)
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@ -189,11 +194,12 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid ))
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misaAccess(CSR.MISA, xlen-2 -> U"01" , 0 -> U(misaExtensions))
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READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP, 3 -> mip.MSIP)
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READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP)
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READ_WRITE(CSR.MIP, 3 -> mip.MSIP)
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READ_WRITE(CSR.MIE, 11 -> mie.MEIE, 7 -> mie.MTIE, 3 -> mie.MSIE)
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mtvecAccess(CSR.MTVEC , mtvec)
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mepcAccess(CSR.MEPC , mepc)
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mtvecAccess(CSR.MTVEC, mtvec)
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mepcAccess(CSR.MEPC, mepc)
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READ_ONLY(CSR.MSTATUS, 7 -> mstatus.MPIE, 3 -> mstatus.MIE)
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if(mscratchGen) READ_WRITE(CSR.MSCRATCH, mscratch)
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mcauseAccess(CSR.MCAUSE, xlen-1 -> mcause.interrupt, 0 -> mcause.exceptionCode)
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@ -220,6 +226,14 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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val done = ! List(fetch, decode, execute, memory, writeBack).map(_.arbitration.isValid).orR
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}
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//Manage ECALL instructions
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when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){
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pluginExceptionPort.valid := True
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pluginExceptionPort.exceptionCode := 11
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}
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//Aggregate all exception port and remove required instructions
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val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
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val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
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@ -231,7 +245,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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val stagePort = stagePortsInfos.length match{
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case 1 => stagePortsInfos.head.port
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case _ => {
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val groupedPort = Flow(UInt(exceptionCodeWidth bits))
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val groupedPort = Flow(ExceptionCause())
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val valids = stagePortsInfos.map(_.port.valid)
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val codes = stagePortsInfos.map(_.port.payload)
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groupedPort.valid := valids.orR
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@ -244,31 +258,40 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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sortedByStage.head.stage.insert(EXCEPTION) := False
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sortedByStage.head.stage.insert(EXCEPTION_CAUSE).assignDontCare()
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for(portInfo <- sortedByStage; port = portInfo.port ; stage = portInfo.stage){
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when(port.valid){
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stages(indexOf(stage) - 1).arbitration.flushIt := True
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stage.input(EXCEPTION) := True
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stage.input(EXCEPTION_CAUSE) := port.payload
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}
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}
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} else null
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val interrupt = False
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val exception = if(exceptionPortsInfos.nonEmpty)
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writeBack.arbitration.isValid && writeBack.input(EXCEPTION)
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else
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False
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when(mstatus.MIE){
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pipelineLiberator.enable := interrupt
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when(exception || (interrupt && pipelineLiberator.done)){
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jumpInterface.valid := True
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jumpInterface.payload := mtvec
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mstatus.MIE := False
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mstatus.MPIE := mstatus.MIE
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mepc := exception ? writeBack.input(PC) | prefetch.input(PC_CALC_WITHOUT_JUMP)
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}
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val interrupt = ((mip.MSIP && mie.MSIE) || (mip.MEIP && mie.MEIE) || (mip.MTIP && mie.MTIE)) && mstatus.MIE
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val exception = if(exceptionPortsInfos.nonEmpty) writeBack.arbitration.isValid && writeBack.input(EXCEPTION) else False
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//Interrupt/Exception entry logic
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pipelineLiberator.enable setWhen interrupt
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when(exception || (interrupt && pipelineLiberator.done)){
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jumpInterface.valid := True
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jumpInterface.payload := mtvec
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mstatus.MIE := False
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mstatus.MPIE := mstatus.MIE
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mepc := exception ? writeBack.input(PC) | prefetch.input(PC_CALC_WITHOUT_JUMP)
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mcause.interrupt := interrupt
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mcause.exceptionCode := interrupt.mux(
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True -> ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))),
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False -> writeBack.input(EXCEPTION_CAUSE).exceptionCode
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)
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}
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//Interrupt/Exception exit logic
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when(memory.arbitration.isFiring && memory.input(ENV_CTRL) === EnvCtrlEnum.MRET){
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jumpInterface.valid := True
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jumpInterface.payload := mepc
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@ -276,15 +299,14 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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}
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//CSR read/write instructions management
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execute plug new Area {
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import execute._
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val imm = IMM(input(INSTRUCTION))
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val writeEnable = !((input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
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|| (input(INSTRUCTION)(14 downto 13) === "10" && imm.z === 0))
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|| (input(INSTRUCTION)(14 downto 13) === "10" && imm.z === 0))
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val readEnable = input(INSTRUCTION)(rdRange) =/= 0
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val writeSrc = input(INSTRUCTION)(14) ? imm.z.asBits.resized | input(SRC1)
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@ -301,6 +323,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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}
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//Translation of the csrMapping into real logic
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val csrAddress = input(INSTRUCTION)(csrRange)
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when(arbitration.isValid && input(IS_CSR)) {
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for ((address, jobs) <- csrMapping.mapping) {
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@ -308,14 +331,12 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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when(writeEnable) {
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for (element <- jobs) element match {
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case element: CsrWrite => element.that.assignFromBits(writeData(element.bitOffset, element.that.getBitsWidth bits))
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// case element: BusSlaveFactoryOnWriteAtAddress => element.doThat()
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case _ =>
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}
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}
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for (element <- jobs) element match {
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case element: CsrRead => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits
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// case element: BusSlaveFactoryOnReadAtAddress => when(readEnable) { element.doThat() }
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case _ =>
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}
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}
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@ -13,6 +13,10 @@ trait DecoderService{
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def addDefault(key : Stageable[_ <: BaseType], value : Any)
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}
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case class ExceptionCause() extends Bundle{
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val exceptionCode = UInt(4 bits)
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}
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trait ExceptionService{
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def newExceptionPort(stage : Stage) : Flow[UInt]
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def newExceptionPort(stage : Stage) : Flow[ExceptionCause]
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}
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