Merge remote-tracking branch 'origin/sim'

This commit is contained in:
Dolu1990 2017-12-17 17:57:51 +01:00
commit f5a1793ef5
7 changed files with 204 additions and 3 deletions

2
.gitignore vendored
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@ -42,3 +42,5 @@ obj_dir
*.tcl
*.o
*verilatorSim/

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@ -4,12 +4,15 @@ organization := "com.github.spinalhdl"
version := "1.0"
scalaVersion := "2.11.8"
scalaVersion := "2.11.6"
EclipseKeys.withSource := true
libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.5",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.5",
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.0",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.0",
"org.yaml" % "snakeyaml" % "1.8"
)
addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
scalacOptions += "-P:continuations:enable"

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@ -127,6 +127,7 @@ object MuraxConfig{
bypassWriteBack = true,
bypassWriteBackBuffer = true
)
// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrielShifterPlugin()
config
}

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@ -0,0 +1,95 @@
package vexriscv
import spinal.sim._
import spinal.core._
import spinal.core.SimManagedApi._
import vexriscv.demo.{Murax, MuraxConfig}
import java.awt.Graphics
import javax.swing.{JFrame, JPanel}
object MuraxSim {
def main(args: Array[String]): Unit = {
// val config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut =>
val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
val jtagClkPeriod = mainClkPeriod*4
val uartBaudRate = 115200
val uartBaudPeriod = (1e12/uartBaudRate).toLong
val genClock = fork{
dut.io.asyncReset #= true
dut.io.mainClk #= false
sleep(mainClkPeriod)
dut.io.asyncReset #= false
sleep(mainClkPeriod)
var cycleCounter = 0l
var lastTime = System.nanoTime()
while(true){
dut.io.mainClk #= false
sleep(mainClkPeriod/2)
dut.io.mainClk #= true
sleep(mainClkPeriod/2)
cycleCounter += 1
if(cycleCounter == 100000){
val currentTime = System.nanoTime()
println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
lastTime = currentTime
cycleCounter = 0
}
}
}
val tcpJtag = TcpJtag(
jtag = dut.io.jtag,
jtagClkPeriod = jtagClkPeriod
)
val uartTx = UartDecoder(
uartPin = dut.io.uart.txd,
baudPeriod = uartBaudPeriod
)
val uartRx = UartEncoder(
uartPin = dut.io.uart.rxd,
baudPeriod = uartBaudPeriod
)
val leds = fork{
var ledsValue = 0l
val ledsFrame = new JFrame{
setContentPane(new DrawPane());
setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE);
setSize(400, 400);
setVisible(true);
//create a component that you can actually draw on.
class DrawPane extends JPanel{
override def paintComponent(g : Graphics) : Unit = {
for(i <- 0 to 7) {
if (((ledsValue >> i) & 1) != 0) {
g.fillRect(20*i, 20, 20, 20)
}
}
}
}
}
while(true){
sleep(mainClkPeriod*100000)
ledsValue = dut.io.gpioA.write.toLong
ledsFrame.repaint()
}
}
genClock.join()
}
}
}

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@ -0,0 +1,43 @@
package vexriscv
import java.io.{InputStream, OutputStream}
import java.net.ServerSocket
import spinal.core.SimManagedApi._
import spinal.lib.com.jtag.Jtag
import scala.concurrent.Future
import scala.concurrent.ExecutionContext.Implicits.global
object TcpJtag {
def apply(jtag: Jtag, jtagClkPeriod: Long) = fork {
var inputStream: InputStream = null
var outputStream: OutputStream = null
val server = Future {
val socket = new ServerSocket(7894)
println("WAITING FOR TCP JTAG CONNECTION")
while (true) {
val connection = socket.accept()
connection.setTcpNoDelay(true)
outputStream = connection.getOutputStream()
inputStream = connection.getInputStream()
println("TCP JTAG CONNECTION")
}
}
while (true) {
sleep(jtagClkPeriod * 200)
while (inputStream != null && inputStream.available() != 0) {
val buffer = inputStream.read()
jtag.tms #= (buffer & 1) != 0;
jtag.tdi #= (buffer & 2) != 0;
jtag.tck #= (buffer & 8) != 0;
if ((buffer & 4) != 0) {
outputStream.write(if (jtag.tdo.toBoolean) 1 else 0)
}
sleep(jtagClkPeriod / 2)
}
}
}
}

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@ -0,0 +1,29 @@
package vexriscv
import spinal.sim._
import spinal.core.SimManagedApi._
import spinal.core.{Bool, assert}
object UartDecoder {
def apply(uartPin : Bool, baudPeriod : Long) = fork{
waitUntil(uartPin.toBoolean == true)
while(true) {
waitUntil(uartPin.toBoolean == false)
sleep(baudPeriod/2)
assert(uartPin.toBoolean == false)
sleep(baudPeriod)
var buffer = 0
(0 to 7).suspendable.foreach{ bitId =>
if(uartPin.toBoolean)
buffer |= 1 << bitId
sleep(baudPeriod)
}
assert(uartPin.toBoolean == true)
print(buffer.toChar)
}
}
}

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@ -0,0 +1,28 @@
package vexriscv
import spinal.sim._
import spinal.core.Bool
import spinal.core.SimManagedApi._
object UartEncoder {
def apply(uartPin : Bool, baudPeriod : Long) = fork{
uartPin #= true
while(true) {
if(System.in.available() != 0){
val buffer = System.in.read()
uartPin #= false
sleep(baudPeriod)
(0 to 7).suspendable.foreach{ bitId =>
uartPin #= ((buffer >> bitId) & 1) != 0
sleep(baudPeriod)
}
uartPin #= true
sleep(baudPeriod)
} else {
sleep(baudPeriod * 10)
}
}
}
}