mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-24 05:57:07 -04:00
Merge remote-tracking branch 'origin/sim'
This commit is contained in:
commit
f5a1793ef5
7 changed files with 204 additions and 3 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -42,3 +42,5 @@ obj_dir
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*.tcl
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*.o
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*verilatorSim/
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@ -4,12 +4,15 @@ organization := "com.github.spinalhdl"
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version := "1.0"
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scalaVersion := "2.11.8"
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scalaVersion := "2.11.6"
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EclipseKeys.withSource := true
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libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.5",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.5",
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.0",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.0",
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"org.yaml" % "snakeyaml" % "1.8"
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)
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addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
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scalacOptions += "-P:continuations:enable"
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@ -127,6 +127,7 @@ object MuraxConfig{
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bypassWriteBack = true,
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bypassWriteBackBuffer = true
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)
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// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrielShifterPlugin()
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config
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}
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95
src/test/scala/vexriscv/MuraxSim.scala
Normal file
95
src/test/scala/vexriscv/MuraxSim.scala
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@ -0,0 +1,95 @@
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package vexriscv
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import spinal.sim._
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import spinal.core._
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import spinal.core.SimManagedApi._
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import vexriscv.demo.{Murax, MuraxConfig}
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import java.awt.Graphics
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import javax.swing.{JFrame, JPanel}
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object MuraxSim {
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def main(args: Array[String]): Unit = {
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// val config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
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val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
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SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut =>
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val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
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val jtagClkPeriod = mainClkPeriod*4
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val uartBaudRate = 115200
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val uartBaudPeriod = (1e12/uartBaudRate).toLong
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val genClock = fork{
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dut.io.asyncReset #= true
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dut.io.mainClk #= false
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sleep(mainClkPeriod)
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dut.io.asyncReset #= false
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sleep(mainClkPeriod)
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var cycleCounter = 0l
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var lastTime = System.nanoTime()
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while(true){
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dut.io.mainClk #= false
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sleep(mainClkPeriod/2)
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dut.io.mainClk #= true
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sleep(mainClkPeriod/2)
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cycleCounter += 1
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if(cycleCounter == 100000){
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val currentTime = System.nanoTime()
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println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
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lastTime = currentTime
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cycleCounter = 0
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}
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}
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}
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val tcpJtag = TcpJtag(
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jtag = dut.io.jtag,
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jtagClkPeriod = jtagClkPeriod
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)
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val uartTx = UartDecoder(
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uartPin = dut.io.uart.txd,
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baudPeriod = uartBaudPeriod
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)
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val uartRx = UartEncoder(
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uartPin = dut.io.uart.rxd,
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baudPeriod = uartBaudPeriod
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)
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val leds = fork{
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var ledsValue = 0l
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val ledsFrame = new JFrame{
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setContentPane(new DrawPane());
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setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE);
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setSize(400, 400);
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setVisible(true);
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//create a component that you can actually draw on.
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class DrawPane extends JPanel{
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override def paintComponent(g : Graphics) : Unit = {
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for(i <- 0 to 7) {
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if (((ledsValue >> i) & 1) != 0) {
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g.fillRect(20*i, 20, 20, 20)
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}
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}
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}
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}
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}
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while(true){
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sleep(mainClkPeriod*100000)
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ledsValue = dut.io.gpioA.write.toLong
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ledsFrame.repaint()
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}
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}
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genClock.join()
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}
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}
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}
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43
src/test/scala/vexriscv/TcpJtag.scala
Normal file
43
src/test/scala/vexriscv/TcpJtag.scala
Normal file
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package vexriscv
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import java.io.{InputStream, OutputStream}
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import java.net.ServerSocket
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import spinal.core.SimManagedApi._
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import spinal.lib.com.jtag.Jtag
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import scala.concurrent.Future
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import scala.concurrent.ExecutionContext.Implicits.global
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object TcpJtag {
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def apply(jtag: Jtag, jtagClkPeriod: Long) = fork {
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var inputStream: InputStream = null
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var outputStream: OutputStream = null
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val server = Future {
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val socket = new ServerSocket(7894)
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println("WAITING FOR TCP JTAG CONNECTION")
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while (true) {
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val connection = socket.accept()
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connection.setTcpNoDelay(true)
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outputStream = connection.getOutputStream()
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inputStream = connection.getInputStream()
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println("TCP JTAG CONNECTION")
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}
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}
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while (true) {
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sleep(jtagClkPeriod * 200)
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while (inputStream != null && inputStream.available() != 0) {
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val buffer = inputStream.read()
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jtag.tms #= (buffer & 1) != 0;
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jtag.tdi #= (buffer & 2) != 0;
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jtag.tck #= (buffer & 8) != 0;
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if ((buffer & 4) != 0) {
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outputStream.write(if (jtag.tdo.toBoolean) 1 else 0)
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}
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sleep(jtagClkPeriod / 2)
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}
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}
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}
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}
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29
src/test/scala/vexriscv/UartDecoder.scala
Normal file
29
src/test/scala/vexriscv/UartDecoder.scala
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package vexriscv
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import spinal.sim._
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import spinal.core.SimManagedApi._
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import spinal.core.{Bool, assert}
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object UartDecoder {
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def apply(uartPin : Bool, baudPeriod : Long) = fork{
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waitUntil(uartPin.toBoolean == true)
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while(true) {
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waitUntil(uartPin.toBoolean == false)
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sleep(baudPeriod/2)
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assert(uartPin.toBoolean == false)
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sleep(baudPeriod)
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var buffer = 0
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(0 to 7).suspendable.foreach{ bitId =>
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if(uartPin.toBoolean)
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buffer |= 1 << bitId
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sleep(baudPeriod)
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}
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assert(uartPin.toBoolean == true)
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print(buffer.toChar)
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}
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}
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}
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28
src/test/scala/vexriscv/UartEncoder.scala
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28
src/test/scala/vexriscv/UartEncoder.scala
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package vexriscv
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import spinal.sim._
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import spinal.core.Bool
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import spinal.core.SimManagedApi._
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object UartEncoder {
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def apply(uartPin : Bool, baudPeriod : Long) = fork{
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uartPin #= true
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while(true) {
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if(System.in.available() != 0){
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val buffer = System.in.read()
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uartPin #= false
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sleep(baudPeriod)
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(0 to 7).suspendable.foreach{ bitId =>
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uartPin #= ((buffer >> bitId) & 1) != 0
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sleep(baudPeriod)
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}
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uartPin #= true
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sleep(baudPeriod)
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} else {
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sleep(baudPeriod * 10)
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}
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}
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}
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}
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