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  • 1fbb81a4d9 regression fix delete [] #46 Dolu1990 2018-12-09 15:40:02 +01:00
  • cf80c63c22 fix travis Dolu1990 2018-12-08 15:16:17 +01:00
  • f121ce1ed5 add sanity asserts in regression #46 Dolu1990 2018-12-08 14:10:18 +01:00
  • 9330945623 fix regression makefile Dolu1990 2018-12-07 23:50:13 +01:00
  • 52419fd7ad Regression remove dplus stuff #46 Dolu1990 2018-12-07 23:47:49 +01:00
  • 68fdbe60cc verilator regression fix missing fclose #46 Dolu1990 2018-12-07 23:43:19 +01:00
  • 6334f430fe
         Update README.md Dolu1990 2018-12-04 19:07:51 +01:00
  • eca54585b0 Fix hardware breakpoint Dolu1990 2018-12-04 16:57:24 +01:00
  • ac1ed40b80 Move things into SpinalHDL lib Dolu1990 2018-12-01 18:25:18 +01:00
  • 3d71045159 DebugPlugin doesn't require memory/writeback stage anymore Dolu1990 2018-12-01 18:24:33 +01:00
  • 58d7a4784d move HexTools into SpinalHDL lib Dolu1990 2018-11-30 17:39:33 +01:00
  • b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus Move PipelinedMemoryBus into SpinalHDL lib Dolu1990 2018-11-30 17:37:17 +01:00
  • f54865bcb8 Merge remote-tracking branch 'origin/dev' 1.0.1 Dolu1990 2018-11-29 22:43:26 +01:00
  • 2f6a2dfccc Add configs setup in SimpleBusInterconnect Dolu1990 2018-11-29 16:14:41 +01:00
  • 7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage Dolu1990 2018-11-24 13:38:54 +01:00
  • c2b9544794 Allow iBusCached plugin to be used when no memory stage is present Dolu1990 2018-11-24 13:37:53 +01:00
  • 2d8d3d0566 Update readme Dolu1990 2018-11-22 22:49:16 +01:00
  • f18696357f SpinalHDL 1.2.2 Dolu1990 2018-11-22 22:45:07 +01:00
  • 0086de9e36 Fix CsrPlugin catch illegalAccess Add dhrystone optimized divider cleaning Dolu1990 2018-11-20 19:39:17 +01:00
  • 75d4d049d7 Add shadow regfile various cleaning Dolu1990 2018-11-16 17:06:11 +01:00
  • cc48fc7403 add fenceiGenAsANop Dolu1990 2018-11-13 15:17:35 +01:00
  • 0d92a5e5cd Add many little options to reduce area Dolu1990 2018-11-12 14:14:34 +01:00
  • fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) Dolu1990 2018-11-09 05:41:43 +01:00
  • b12e15b112 branch/csr/muldiv minor improvments Dolu1990 2018-11-07 19:27:49 +01:00
  • b7f3ee5e06 Fix CsrPlugin pipelined option Dolu1990 2018-11-05 16:22:41 +01:00
  • 662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) Dolu1990 2018-11-03 11:29:30 +01:00
  • 978232fd63 Optimise div iterative plugin done signal Dolu1990 2018-11-03 11:12:37 +01:00
  • c8ac214097 Optimize CSR Dolu1990 2018-10-28 02:18:27 +02:00
  • 51de2b5820 SimpleBusInterconnect now adapte address width Dolu1990 2018-10-28 02:18:08 +02:00
  • 00bf84b7f8 Add SimpleBusInterconnect Dolu1990 2018-10-25 23:47:05 +02:00
  • 4ed4af6a3e SrcPlugin add decodeAddSub option Dolu1990 2018-10-24 01:28:37 +02:00
  • 372063582c Improve CsrPlugin CombinatorialPaths Dolu1990 2018-10-23 19:07:08 +02:00
  • 7096c63d50 Add more SimpleBus utilies Dolu1990 2018-10-23 17:46:31 +02:00
  • 7c0f2dc713 Add SimpleBus object Dolu1990 2018-10-20 12:39:20 +02:00
  • 85e696b286 CsrPlugin : Add mtvecModeGen Morard Dany 2018-10-16 14:53:41 +02:00
  • 1e64d71609 Merge remote-tracking branch 'origin/Supervisor' into dev Dolu1990 2018-10-16 13:09:17 +02:00
  • 905abd5aaa Add wfiGenAsWait and wfiGenAsNop CsrPlugin cleaning Much cleaning in general Zephyr is running Supervisor Dolu1990 2018-10-16 13:07:30 +02:00
  • 25c0a0ff6f
         Add RVC into the readme Dolu1990 2018-10-13 09:57:13 +02:00
  • f903df4b66 sync Dolu1990 2018-10-12 17:13:54 +02:00
  • 2b29690010 Clean branch plugin lsb bit calculation BranchPlugin doesn't try anymore to catch exception when RVC is on Dolu1990 2018-10-12 12:24:52 +02:00
  • eea92154ae fetcher force PC LSB to be zero Dolu1990 2018-10-12 12:02:52 +02:00
  • 0b8f6f6ed4 Fix broken C.LWSP reference_output Dolu1990 2018-10-12 12:02:02 +02:00
  • 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test Dolu1990 2018-10-11 22:19:17 +02:00
  • 8c25e73b9d Fix DIV negative values divided by zero Dolu1990 2018-10-11 22:18:21 +02:00
  • c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned Dolu1990 2018-10-11 17:56:49 +02:00
  • 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval Dolu1990 2018-10-11 00:25:39 +02:00
  • 40d85b8c70 Add fenceiGenAsAJump into BranchPlugin Dolu1990 2018-10-10 21:13:21 +02:00
  • 68f1ff3222 Add CsrPlugin ebreak support Dolu1990 2018-10-10 19:23:04 +02:00
  • 0662cc2797 Add GenMicro experiment to reduce ice40 area usage. IBusSimplePlugin now require cmdFork parameters to be set (no default) Dolu1990 2018-10-03 22:08:57 +02:00
  • 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) IBusSimplePlugin now implement cmdForkPersistence option Dolu1990 2018-10-03 16:24:10 +02:00
  • c61f17aea3 Fetcher/IBusSimplePlugin wip Dolu1990 2018-10-03 01:02:22 +02:00
  • 0ada869b2d regression golden ref regfile is now sync with trl boot's random values wip Dolu1990 2018-10-01 16:14:21 +02:00
  • 65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling (uncached DBus TODO) Dolu1990 2018-10-01 12:13:05 +02:00
  • 7770eefa3b wip Dolu1990 2018-09-30 12:57:08 +02:00
  • 39c6bc11d6 Pass basic regression again Dolu1990 2018-09-29 19:04:20 +02:00
  • 5ad7c39f47 wip Dolu1990 2018-09-29 12:04:58 +02:00
  • 37a1970ad6 wip Dolu1990 2018-09-28 16:02:33 +02:00
  • 32cf90a162 Merge remote-tracking branch 'origin/dev' into Supervisor Dolu1990 2018-09-27 22:16:49 +02:00
  • 992c21ddd1 fix travis Dolu1990 2018-09-27 19:06:33 +02:00
  • 9a3510f63d Map all supervisor registers Dolu1990 2018-09-27 19:03:57 +02:00
  • acd1ca422a wip Dolu1990 2018-09-27 18:24:40 +02:00
  • a2d3cfbfc1 Remove unused file Dolu1990 2018-09-27 00:56:20 +02:00
  • 6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL Dolu1990 2018-09-27 00:55:30 +02:00
  • aff436ddcf Sync with SpinalHDL head Add mmu test into the dhrystone regression command Dolu1990 2018-09-24 18:31:33 +02:00
  • 1e3b75ef1d xip typo Dolu1990 2018-09-23 22:06:21 +02:00
  • 86efb75f6a rework fetcher Dolu1990 2018-09-23 22:05:53 +02:00
  • 56fd73fbbc Add missing bin files Dolu1990 2018-09-23 19:26:11 +02:00
  • bdc3246f5a Fix xip gitignore Dolu1990 2018-09-23 19:23:43 +02:00
  • 5024cc5616 Hardware breakpoint feature added Murax XIP debugging passed tests Dolu1990 2018-09-20 13:11:20 +02:00
  • ff1d1072a7 XIP is physicaly working on murax Dolu1990 2018-09-19 00:09:14 +02:00
  • b51ac03a5e murax xip flash integration wip Dolu1990 2018-09-18 16:53:26 +02:00
  • 3e17461cc7 Add optional XIP to Murax Dolu1990 2018-09-16 11:00:56 +02:00
  • 312e8b99b8 Merge remote-tracking branch 'origin/master' into dev Dolu1990 2018-09-16 10:21:31 +02:00
  • fc1f4ec23a Merge remote-tracking branch 'origin/spinal_1.1.7' Dolu1990 2018-09-16 10:17:41 +02:00
  • 0476de8066 Move to SpinalHDL 1.2.0 spinal_1.1.7 Dolu1990 2018-09-16 10:16:43 +02:00
  • 44bbfff4d4
         Update README.md Dolu1990 2018-09-14 11:30:26 +02:00
  • d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters Dolu1990 2018-09-11 16:08:28 +02:00
  • 791608f655 Move swing stuff into main test package Dolu1990 2018-08-29 14:55:25 +02:00
  • 0255f51cc5 Add unpipelined Wishbone support for uncached version Dolu1990 2018-08-24 12:20:14 +02:00
  • 304c8156a0
         Update version Snoopy87 2018-08-24 06:51:10 +02:00
  • 39e1791067 Merge remote-tracking branch 'origin/dev' 1.0.0 Dolu1990 2018-08-23 01:23:43 +02:00
  • 7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation Dolu1990 2018-08-22 02:08:55 +02:00
  • 38af5dbdd5 riscv emulator WIP (RVC missing) Dolu1990 2018-08-21 01:03:51 +02:00
  • dca1e5f438 revert RVC from murax Dolu1990 2018-08-17 23:12:45 +02:00
  • f8c8643aa5 Merge remote-tracking branch 'origin/reworkFetcher' Dolu1990 2018-08-17 21:26:00 +02:00
  • 8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher Dolu1990 2018-08-17 20:56:51 +02:00
  • 9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids Dolu1990 2018-08-17 20:38:33 +02:00
  • 819da2d0b4 remove freertos from travisautomated regressions tests Dolu1990 2018-08-17 20:07:09 +02:00
  • 1d3ac7830b restore tests without CSR catch all Dolu1990 2018-08-17 19:33:41 +02:00
  • 330ee14a23 final fetchRework commit ? Dolu1990 2018-08-17 19:13:23 +02:00
  • 91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue Dolu1990 2018-08-14 11:51:53 +02:00
  • ae85698a2b MulSimple Tom Verbeure 2018-08-09 22:15:26 -07:00
  • 7ab04a128d
         Merge pull request #34 from mithro/master Dolu1990 2018-07-21 18:38:57 +02:00
  • 50f6836100
         Merge pull request #29 from mcmasterg/sudo_newline Dolu1990 2018-07-21 18:10:21 +02:00
  • 373a3fcb90 README: Small improvement to text. Tim 'mithro' Ansell 2018-07-21 09:08:29 -07:00
  • ccde67bb67 README: Strip trailing white space. Tim 'mithro' Ansell 2018-07-21 09:03:22 -07:00
  • 53cde3731b
         Merge pull request #33 from mithro/master Dolu1990 2018-07-21 12:33:53 +02:00
  • dbda31ad15
         Merge pull request #30 from mithro/mithro-patch-1 Dolu1990 2018-07-21 12:15:29 +02:00
  • 1c5ee779ef Generate Murax with the flashy program. Tim 'mithro' Ansell 2018-07-20 19:04:59 -07:00
  • acbce9fb57 Adding a README file with images. Tim 'mithro' Ansell 2018-07-20 19:04:41 -07:00