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BrieyAxi64

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Wishbone

areaOpt

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cfu

cfuFix

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dBusCachedRelaxMmuTranslation

debug-debug

debugPlugin

dev

dev_1.6.2

fiber

formal

fpu

fpu-fixes

linux

linuxDev

litex-privileged-debug

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masterPrerelease

pipelinedInterrupt

reworkInstructionCache

rework_fetch

rework_jump_flush

riscv-debug

rpls-mul16

short-pipeline-fixes

sim

smp

spinal_1.1.7

spinal_1.4.4

spinalhdl_reworkDev

tigthlyCoupled

tmp

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1.0.0

1.0.1

Mono Color

• c49373f3d1 Fix missing JAL, JALR encoding Charles Papon 2017-03-21 10:29:09 +01:00
• 787682d4f6 Add comments Some refractoring Charles Papon 2017-03-20 14:49:49 +01:00
• 51058f851e Renaming Charles Papon 2017-03-20 12:37:53 +01:00
• ecf853f491 Add Static/Dynamic branch prediction Charles Papon 2017-03-20 12:37:20 +01:00
• d569242124 Add Static branch prediction in decode stage Charles Papon 2017-03-19 23:27:35 +01:00
• 88dee6d2bc Reduce area with reg[0] optimisation Charles Papon 2017-03-18 19:32:54 +01:00
• fc1bb7249a Add trace option to regresion Charles Papon 2017-03-18 14:06:42 +01:00
• 5e9da0f27a Add self checked dhrystone test Charles Papon 2017-03-18 12:32:14 +01:00
• 31db6511dc Fix performance of removed instruction which halt were halting the pipeline Charles Papon 2017-03-18 10:51:55 +01:00
• 20ca348707 Fix dCmd sent while the execute stage is removed Pass dhrystone benchmark without error ! Charles Papon 2017-03-17 21:26:42 +01:00
• 7517ac797d Add MUL/DIV/REM support with plugins (pass Riscv-Tests) Charles Papon 2017-03-17 11:45:01 +01:00
• 52a524be06 Add light shifter plugin Charles Papon 2017-03-16 15:11:06 +01:00
• 401be6ca83 Reorganize project Charles Papon 2017-03-16 13:14:25 +01:00
• bf5bebda08 PcManager now drive PC asyncronously (use 1 cycle less in jump) Fix bypass logic when read/write r0 Disable REGFILE_WRITE_VALID in decod stage when r0 is written Charles Papon 2017-03-15 21:10:44 +01:00
• 83232e9860 Faster pipeline arbitration logic (200 Mhz on cyclone IV c6) Branch plugin with jump in execute or memory stages (parameter) Charles Papon 2017-03-15 20:02:56 +01:00
• c6610ea454 Fix halt arbitrations Charles Papon 2017-03-15 17:14:58 +01:00
• 11797fbb6e Add sim performance print Charles Papon 2017-03-14 23:25:04 +01:00
• 70d910e7d7 Load/Store pass Riscv-Tests Charles Papon 2017-03-14 23:00:24 +01:00
• 7065ed5d93 All base instruction pass Riscv-Test (load/store not tested) Charles Papon 2017-03-14 20:13:35 +01:00
• ad6964f0bb Classify tests Riscv-test integration wip Charles Papon 2017-03-14 00:42:48 +01:00
• df99a0d963 Better decoding Charles Papon 2017-03-13 18:30:37 +01:00
• e36c90af03 Add decoder bench Charles Papon 2017-03-13 16:17:57 +01:00
• 9fc82c9736 Pass verilator simple literal, add, jump Charles Papon 2017-03-12 20:12:40 +01:00
• ec4837a744 wip Dolu1990 2017-03-12 12:39:33 +01:00
• cb1b73bc2b Add branch Dolu1990 2017-03-11 19:07:08 +01:00
• 23abdb7f95 Add hazard tracking plugin Dolu1990 2017-03-11 16:45:04 +01:00
• e58f28bc27 Add store/load Dolu1990 2017-03-11 15:35:56 +01:00
• fcb70a333f WIP Dolu1990 2017-03-11 00:34:49 +01:00
• fc7e9a7730 wip Dolu1990 2017-03-09 01:07:55 +01:00
• 130ed6345c boot Dolu1990 2017-03-08 22:17:48 +01:00