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  • d7e9c726c3 Fix datacache initial flush Dolu1990 2023-02-23 14:42:21 +01:00
  • c5689e512c CsrPlugin now provide regression args Dolu1990 2023-02-23 12:00:25 +01:00
  • a40d5f19b2 Fix MMU A and D flag handeling Dolu1990 2023-02-23 12:00:08 +01:00
  • 344b2d4eda TestIndividual supervisor missing CSR=yes Dolu1990 2023-02-23 11:59:13 +01:00
  • 9605b663bf D$ now support thightly coupled ram. Add IBusDBusCachedTightlyCoupledRam plugin Dolu1990 2023-02-22 15:26:14 +01:00
  • 220b599c9a Fix d$ invalidation when the mmu is enabled Dolu1990 2023-02-22 13:15:57 +01:00
  • bbbfc7ee6b fix too early riscv-debug Dolu1990 2023-02-19 09:51:18 +01:00
  • 1c38b6ec66 fix too early Dolu1990 2023-02-19 09:48:59 +01:00
  • 366f09a14a fix too early Dolu1990 2023-02-19 09:51:18 +01:00
  • 15a665af53 fix too early Dolu1990 2023-02-19 09:51:18 +01:00
  • c57da3c7dc fix too early Dolu1990 2023-02-19 09:50:41 +01:00
  • d078297496 fix too early Dolu1990 2023-02-19 09:48:59 +01:00
  • a780eec616 Merge branch 'debug-debug' into dev Dolu1990 2023-02-13 10:04:41 +01:00
  • 33e820bdf9 FPU now implement a less pessismitic dirty logic Dolu1990 2023-02-08 15:16:53 +01:00
  • 3ae51cdeb8 Fix fpu csr access on fs===0 now also trap Dolu1990 2023-02-08 14:44:04 +01:00
  • 692f604dd5 Fix VexRiscvSmpClusterGen without linux debug minimal features debug-debug Dolu1990 2023-02-08 11:28:21 +01:00
  • cbc89093b3 fpu csr access on fs===0 now also trap Dolu1990 2023-02-07 10:18:08 +01:00
  • 9acc5ddc1c Fix FPU access trap on fs = 0 #297 Dolu1990 2023-02-06 11:44:44 +01:00
  • fc9a9d25ed sync Dolu1990 2023-02-06 11:43:49 +01:00
  • e83bc5312e Fix RVC decompressor don't care #296 Dolu1990 2023-01-18 15:19:33 +01:00
  • 2bc6e70f03 Fix RVC decompressor don't care #296 Dolu1990 2023-01-18 15:19:33 +01:00
  • 7d3a862183 Fix Litex cluster scopt update Dolu1990 2023-01-16 18:10:51 +01:00
  • aea2e90d1e Upgrade to SBT 1.6.0 Dolu1990 2023-01-16 17:58:23 +01:00
  • 94f2ea6dec
         Merge pull request #289 from buncram/expose-satp Dolu1990 2023-01-16 12:45:02 +01:00
  • 0aa6e0573d
         shorter satp export Dolu1990 2023-01-16 12:43:01 +01:00
  • ed5babaaab
         shorter syntax on privilege export Dolu1990 2023-01-16 12:39:55 +01:00
  • 2297f8aea0 also need to expose privilege state buncram 2023-01-16 02:16:25 +08:00
  • 0963eb06bd
         Merge pull request #294 from chiangkd/master Dolu1990 2023-01-13 16:25:30 +01:00
  • 6650d0549d Fix invalid hyperlink chiangkd 2023-01-12 20:51:58 +08:00
  • c8dff13391
         Merge pull request #291 from chiangkd/master Dolu1990 2023-01-02 09:56:49 +01:00
  • df52fab7d1 Fix incorrect comment chiangkd 2022-12-24 20:41:57 +08:00
  • 8a6a926401
         Merge pull request #288 from betrusted-io/expand-satp Dolu1990 2022-12-20 16:05:13 +01:00
  • 11f391eadf Merge remote-tracking branch 'origin/expand-satp' into expose-satp buncram 2022-12-20 19:31:15 +08:00
  • bf3521f86a Expand SATP register to 22 bits per spec bunnie 2022-12-20 19:25:47 +08:00
  • b86047901a add flag to expose SATP externally buncram 2022-12-19 19:03:33 +08:00
  • 51b69a1527 SpinalHDL 1.8.0 Dolu1990 2022-12-05 20:10:58 +01:00
  • 773f268f37 Fix FPU test syntax Dolu1990 2022-12-01 12:04:13 +01:00
  • fb084327da Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert Dolu1990 2022-11-28 16:30:47 +01:00
  • eafeb5fe49 Add EmbeddedRiscvJtag.debugCd Dolu1990 2022-11-28 11:04:02 +01:00
  • a25ae96d33 comment debug code Dolu1990 2022-11-21 14:02:35 +01:00
  • 572ca3fcfa Privileged debug fake maskmax to 31 Dolu1990 2022-11-21 14:01:28 +01:00
  • 5a8cdee884 Fix CsrPlugin dcsr.stepie Dolu1990 2022-11-21 11:55:05 +01:00
  • 4ae7386904 Merge pull request #276 from LYWalker/master Dolu1990 2022-11-18 17:38:50 +01:00
  • e19e59b55c Clear mprv on xretAwayFromMachine Dolu1990 2022-11-17 15:03:47 +01:00
  • 663174bc73 Privileged debug now implement stoptime stopcount Dolu1990 2022-11-17 13:58:25 +01:00
  • 36c3346e51 ensure rvc 0 is detected as a illegal instruction Dolu1990 2022-11-17 11:03:42 +01:00
  • 5e17ab62d6 Fix RISC-V debug hardware breakpoints Dolu1990 2022-11-14 14:45:11 +01:00
  • fe68b8494e Fix a few RISC-V official debug support : - Disable interrupts in debug mode - Ensure traps do not change CSR in debug mode - step will also consider trapEvent Dolu1990 2022-11-11 14:05:38 +01:00
  • 2504f9b9b9 RISC-V debug havereset implemented Dolu1990 2022-11-10 15:49:03 +01:00
  • 0bfaf06a4a main.cpp add VEXRISCV_JTAG=yes Dolu1990 2022-11-10 13:43:14 +01:00
  • 8b934b4d57 Added a reference to main README LYWalker 2022-11-07 17:27:13 +02:00
  • 526240d1d7 Add README explaining how to add VJTAG LYWalker 2022-11-07 17:11:00 +02:00
  • 71021ead69 Add VJTAG bridge import LYWalker 2022-11-07 17:10:34 +02:00
  • 8a60ebfbab Add VJtag option to Debug Plugin LYWalker 2022-11-06 14:55:59 +02:00
  • f71234786f Remove rv64 opcode (shift and lwu) Thanks Milan Dolu1990 2022-10-27 15:44:50 +02:00
  • d70794f252 fix regression Dolu1990 2022-10-27 15:38:34 +02:00
  • 5d0deb20b3 Fix regression compilation Dolu1990 2022-10-27 15:20:55 +02:00
  • 9f6186cd9a Add GenFullWithRiscvPrivilegedDebugJtag demo Dolu1990 2022-10-27 14:55:40 +02:00
  • 6289ebcbe4 Merge branch 'riscv-debug' into dev Dolu1990 2022-10-27 14:46:46 +02:00
  • a6c29766da CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled Dolu1990 2022-10-26 15:48:26 +02:00
  • ab7b2cff3b fix diagram name Dolu1990 2022-10-26 10:48:21 +02:00
  • 7fd55c7851 Add VexRiscvAxi4LinuxPlicClint diagram drawio Dolu1990 2022-10-26 10:47:23 +02:00
  • 0e531515ac cleaning Dolu1990 2022-10-26 10:25:50 +02:00
  • 63dd787bce VexRiscvAxi4Linux now integrate Plic and Clint Dolu1990 2022-10-26 10:15:21 +02:00
  • 220af95043 Add VexRiscvAxi4Linux (untested, but generate a netlist) Dolu1990 2022-10-24 10:35:59 +02:00
  • 0979f8ba80 Add whitebox example Dolu1990 2022-10-24 10:24:32 +02:00
  • 17d52ce58f privileged debug now access data cache with caching enable Dolu1990 2022-10-21 18:58:40 +02:00
  • 486d17d245 CsrOpensbi now add rvc to misa Dolu1990 2022-10-21 18:58:13 +02:00
  • 662943522f Fix privileged debug trigger decode break logic Dolu1990 2022-10-21 17:21:13 +02:00
  • 95c656ceef riscv debug multiple harts Dolu1990 2022-10-21 12:28:17 +02:00
  • 0313f84419 Fix RISCV debug step Dolu1990 2022-10-20 10:36:30 +02:00
  • 4cd3f65296 Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet) Dolu1990 2022-10-19 12:36:45 +02:00
  • 87c8822f55 Merge branch 'dev' (fix FPU dirty flag on csr write) Dolu1990 2022-10-13 09:35:55 +02:00
  • 959e48a353 Fpu now set csr status fs on FPU csr write Dolu1990 2022-10-06 11:13:57 +02:00
  • 7b9891829a More bus doc #266 Dolu1990 2022-09-26 11:39:58 +02:00
  • 051d140c33 SpinalHDL 1.7.3 Dolu1990 2022-09-19 13:27:22 +02:00
  • fda7da00c2 add litex --wishbone-force-32b Dolu1990 2022-09-06 11:18:48 +02:00
  • e3e21994b4 use SpinalHDL "dev" Dolu1990 2022-07-22 09:33:12 +02:00
  • 54412bde30 getDrivingReg() update Dolu1990 2022-07-21 09:10:23 +02:00
  • 24795ef09b SpinalHDL 1.7.1 Dolu1990 2022-07-20 11:17:10 +02:00
  • a650000f0b SpinalHDL 1.7.2 Dolu1990 2022-07-11 12:02:59 +02:00
  • b1252f47de csr opensbi now enable ebreak Dolu1990 2022-06-13 16:34:49 +02:00
  • 1303c0ca7c CfuPlugin.withEnable added Dolu1990 2022-06-09 17:57:24 +02:00
  • 1ce4c6e493 fix VexRiscvRegressionData url Dolu1990 2022-06-01 09:53:41 +02:00
  • 8ab9a9b12e fix VexRiscvRegressionData url Dolu1990 2022-06-01 09:53:41 +02:00
  • 0f6d0f022c VexRiscvBmbGenerator now also report bytesPerLine Dolu1990 2022-05-24 12:37:31 +02:00
  • 771eaf431e Better cache invalidation doc Dolu1990 2022-05-24 12:15:57 +02:00
  • e6dfcac0be Add D$ single line flush support Dolu1990 2022-05-24 12:13:37 +02:00
  • 4c4913c703 Fix MPP to only retain legal values Dolu1990 2022-05-24 11:14:34 +02:00
  • 209fc719e8 VexRiscvBmbGenerator export more info Dolu1990 2022-05-24 10:19:35 +02:00
  • 48cf4120f2 Add VexRiscvSmpCluster forceMisa/forceMscratch Dolu1990 2022-05-23 15:49:32 +02:00
  • 0872852387 Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254 Dolu1990 2022-05-17 20:44:02 +02:00
  • b39557e226 Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254 Dolu1990 2022-05-17 20:44:02 +02:00
  • a553d3b476 Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254 Dolu1990 2022-05-17 15:27:31 +02:00
  • 8d0f7781de Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254 Dolu1990 2022-05-17 15:27:31 +02:00
  • ba908ebada
         Merge pull request #253 from mmicko/micko/riscv_formal Dolu1990 2022-05-16 11:48:12 +02:00
  • 9c768be7af Fix CfuPlugin/VfuPlugin fork duplication https://github.com/google/CFU-Playground/issues/582 Dolu1990 2022-05-16 10:36:21 +02:00
  • 78f0a7f13e Fix CfuPlugin/VfuPlugin fork duplication https://github.com/google/CFU-Playground/issues/582 Dolu1990 2022-05-16 10:36:21 +02:00
  • 8df2dcbd40 Fix RVC step by step triggering next instruction branch predictor Dolu1990 2022-05-11 14:10:11 +02:00
  • 4fff62d3fe Fix RVC step by step triggering next instruction branch predictor Dolu1990 2022-05-11 14:10:11 +02:00