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  • e0eb00573c SpinalHDL 1.7.0a Dolu1990 2022-05-09 11:33:15 +02:00
  • 6326736401
         Update build.sbt Dolu1990 2022-05-04 00:03:54 +02:00
  • 27772a65dd SpinalHDL 1.7.1 Dolu1990 2022-04-29 15:22:34 +02:00
  • 8d6cb26421 Merge branch 'dev' Dolu1990 2022-04-29 15:20:29 +02:00
  • 9506b0b8f1 SpianlHDL 1.7.0 Dolu1990 2022-04-29 14:16:41 +02:00
  • 9772e6775d
         readme now document FPU / openocd limitations Dolu1990 2022-04-27 16:12:56 +02:00
  • 5fe1fb07d4
         Merge pull request #249 from saahm/master Dolu1990 2022-04-26 14:56:11 +02:00
  • 17007586e8 #241 Fix Murax/Briey TB timeouts Dolu1990 2022-04-11 11:59:41 +02:00
  • bd74833900 add murax peripheral extension tutorial Sallar Ahmadi-Pour 2022-04-25 12:21:41 +02:00
  • 8a8e976493
         Merge pull request #248 from dnltz/WIP/dnltz/fix-reg Dolu1990 2022-04-22 11:12:26 +02:00
  • ea7a18c7f4 plugin: caches: Fix "Can't resolve the literal value of" Daniel Schultz 2022-04-20 11:16:19 +02:00
  • 3b8270b82b #241 Fix Murax/Briey TB timeouts Dolu1990 2022-04-11 11:59:41 +02:00
  • 53d52692de #240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust Dolu1990 2022-04-08 11:09:48 +02:00
  • db34033593 #240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust Dolu1990 2022-04-08 11:09:07 +02:00
  • 32a5206541 Update to latest risc-v-formal Miodrag Milanovic 2022-04-04 16:37:43 +02:00
  • e6c21996a4
         Merge pull request #243 from andreasWallner/fix_gen_simd_add_resetvector Dolu1990 2022-04-04 10:16:50 +02:00
  • 2d2017465e Fix reset vector of GenCustomSimdAdd Andreas Wallner 2022-04-02 18:22:10 +02:00
  • 4abeb6bc3e Fix reset vector of GenCustomSimdAdd Andreas Wallner 2022-04-02 18:22:10 +02:00
  • ccff48f872 deprecated Data.keep Dolu1990 2022-03-30 16:17:57 +02:00
  • 4bddb091ae Update CFU example Dolu1990 2022-03-23 18:58:18 +01:00
  • 5dc91a8be4 Add MuraxCfu Dolu1990 2022-03-23 18:54:18 +01:00
  • b2e61caf9e CfuPlugin now implement upstream spec Dolu1990 2022-03-23 18:54:07 +01:00
  • 9149c42065 DecoderPlugin now implement forceIllegal API Dolu1990 2022-03-23 18:53:43 +01:00
  • 51b8865b66 Fix VexRiscvSmpClusterGen linux less mhartid Dolu1990 2022-03-18 12:36:05 +01:00
  • 6abc6ec194 Fix VexRiscvSmpClusterGen linux less mhartid dev_1.6.2 Dolu1990 2022-03-18 12:34:46 +01:00
  • e1620c68b2 Fix Briey simulation floating rxd blocking the uart #238 Dolu1990 2022-02-22 16:15:14 +01:00
  • e558b79582 Fix Briey simulation floating rxd blocking the uart #238 Dolu1990 2022-02-22 16:15:14 +01:00
  • 9d3b83366c Merge branch 'master' into dev Dolu1990 2022-02-17 16:27:26 +01:00
  • 36f57d5eb7
         Merge pull request #236 from dnltz/WIP/dnltz/remove-assert Dolu1990 2022-02-17 16:25:45 +01:00
  • 5b45ddab1b SpinalHDL 1.6.4 Dolu1990 2022-02-16 14:26:58 +01:00
  • e4fde184d9 SpinalHDL 1.6.5 Dolu1990 2022-02-16 14:12:00 +01:00
  • 807aa98d37 plugin: DBusSimplePlugin: Remove assert Daniel Schultz 2022-02-10 19:55:08 +01:00
  • 77e361e91e Merge branch 'dev' Dolu1990 2022-02-05 12:08:43 +01:00
  • 5714680278 Merge branch 'master' into dev Dolu1990 2022-02-05 11:32:40 +01:00
  • 62c07670af version++ Dolu1990 2022-02-05 11:31:04 +01:00
  • 4dd650736f verilator++ Dolu1990 2022-02-04 16:36:11 +01:00
  • 378c0f8723 verilator++ Dolu1990 2022-02-04 16:20:43 +01:00
  • 8b2f107d46 verilator++ Dolu1990 2022-02-04 15:10:57 +01:00
  • 7d9a50357f
         Merge pull request #233 from dnltz/WIP/dnltz/csr-registers Dolu1990 2022-01-27 12:05:43 +01:00
  • 57dd80a566 plugin: CsrPlugin: Init cycle and instret registers Daniel Schultz 2022-01-26 08:59:03 +01:00
  • 9c34a1fd2e updated related to JtagInstructionWrapper.ignoreWidth Dolu1990 2022-01-14 09:59:22 +01:00
  • b8e904e43f syncronize golden model with dut for lrsc reservation Dolu1990 2022-01-10 19:55:28 +01:00
  • 6e77f32087 sim golden model lrsc reservation sync Dolu1990 2022-01-10 16:08:38 +01:00
  • da53de360f Fix lrsc from last commit Dolu1990 2022-01-10 14:21:20 +01:00
  • f46ad43f39
         DataCache.withInternalLrSc reserved clearing fix Dolu1990 2022-01-10 13:39:41 +01:00
  • 349993b235
         Merge pull request #230 from OscarShiang/typo Dolu1990 2022-01-04 11:02:27 +01:00
  • fe6c391fe4 Fix typo in Linux.scala Oscar Shiang 2022-01-04 16:31:23 +08:00
  • 34e5cafb75 Enable scala 2.13 compatibility Dolu1990 2021-12-20 09:38:02 +01:00
  • 4824827b7e Enable scala 2.13 compatibility Dolu1990 2021-12-20 09:38:02 +01:00
  • a340798840
         Update build.properties Dolu1990 2021-12-18 09:11:08 +01:00
  • 53a3330340
         Update build.properties Dolu1990 2021-12-18 09:10:43 +01:00
  • dd12047aa7 Merge branch dev (SpinalHDL 1.6.1) Dolu1990 2021-12-15 09:22:46 +01:00
  • ea5e7e2a3b Update to SpinalHDL v1.6.1 Daniel Schultz 2021-12-14 17:52:17 +01:00
  • 0539dd7110
         SpinalHDL 1.6.2 Dolu1990 2021-12-08 23:45:05 +01:00
  • 6c5908f7a3
         Merge pull request #220 from BLangOS/patch-1 Dolu1990 2021-11-15 09:25:00 +01:00
  • 411d946a58
         Update DebugPlugin.scala B.Lang 2021-11-11 12:12:23 +01:00
  • acf14385d8 #213 disable pmp test with region overlapping Dolu1990 2021-10-22 17:24:51 +02:00
  • 9df704cad9
         Merge pull request #213 from occheung/pmp-fix Dolu1990 2021-10-21 10:13:21 +02:00
  • a3807660e3 pmp perm: revert to mux for priority occheung 2021-10-19 11:40:39 +08:00
  • df03c99ab2 pmp_setter: fix mask generation occheung 2021-10-19 11:39:25 +08:00
  • c3c3a94c5d IBusSimplePlugin can now use a Vec based buffer Dolu1990 2021-10-13 16:26:16 +02:00
  • 97a3c1955b VexRiscvSmpCluster add d$ i$ less arg Dolu1990 2021-10-08 13:19:01 +02:00
  • 3bd940e89d Briey add memoryDataWidth arguments BrieyAxi64 Dolu1990 2021-10-01 11:42:04 +02:00
  • f118a901dd Add a 64 bits interconnect to Briey Dolu1990 2021-09-28 13:39:59 +02:00
  • 35754a0709 Fix BrieySim (SpinalSim) Dolu1990 2021-09-25 13:28:37 +02:00
  • 8c0fbcadac Add BrieySim (SpinalSim) Dolu1990 2021-09-25 13:18:55 +02:00
  • 5f5f4afbf2 Briey revert RVC unwanted addition Dolu1990 2021-09-22 15:01:08 +02:00
  • b807254759 Briey and Murax verilators now use FST instead of VCD Dolu1990 2021-09-22 12:57:27 +02:00
  • 65cda95176 Fix wishbone bridges with datawidth > 32 Dolu1990 2021-09-17 09:43:30 +02:00
  • c1481ae244 update ScopeProperty usages Dolu1990 2021-09-16 19:08:41 +02:00
  • 42bb1ab591 d$ / i$ toWishbone bridges can now be bigger than 32 bits https://github.com/m-labs/VexRiscv-verilog/pull/12 Dolu1990 2021-09-15 11:36:51 +02:00
  • 68e704f309 restore avalon d$ tests Dolu1990 2021-09-02 15:42:33 +02:00
  • efd3cd4737 Merge branch 'master' into dev Dolu1990 2021-09-02 14:16:07 +02:00
  • cc9f3e753a Fix d$ toAxi bridge Dolu1990 2021-09-02 14:14:42 +02:00
  • bc561c30eb Add PmpPluginOld (support TOR) Dolu1990 2021-09-01 11:27:12 +02:00
  • 5c7e4a0294 #170 wishbone example now set dBusCmdMasterPipe Dolu1990 2021-08-24 23:24:22 +02:00
  • 3deeab42fd VexRiscvSmpCluster config fix Dolu1990 2021-08-10 12:14:39 +02:00
  • 805bd56077 Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value Dolu1990 2021-07-30 16:51:07 +02:00
  • 671bd30953 Update Bmb invalidate/sync parameters Dolu1990 2021-07-28 13:44:04 +02:00
  • ba8f5f966a Vfu typo Dolu1990 2021-07-26 15:27:20 +02:00
  • b717f228d6 VfuPlugin wip Dolu1990 2021-07-26 15:17:06 +02:00
  • c242744d02 CfuPlugin now only fork when the rest of the pipeline is hazard free Dolu1990 2021-07-26 14:45:54 +02:00
  • f3f9b79f9a VexRiscvSmpCluster earlyShifterInjection added Dolu1990 2021-07-21 18:34:57 +02:00
  • 5fc4125763 Merge branch 'dev' Dolu1990 2021-07-20 11:21:11 +02:00
  • 3028c19389 Fix #191 (data cache toAxi bridge) Dolu1990 2021-07-20 11:20:53 +02:00
  • 5f2fcc7d0f Merge branch 'dev' (SpinalHDL 1.6.0) Dolu1990 2021-07-20 10:39:09 +02:00
  • 66bcd7fca7 readme: add the tom link about JTAG and GDB Dolu1990 2021-07-20 10:14:54 +02:00
  • 561c29906e build.sbt: Update to SpinalHDL v1.6 Daniel Schultz 2021-07-12 21:35:00 +02:00
  • 45c0e75313 vexriscv: demo: Add brackets to bool Daniel Schultz 2021-07-12 21:33:24 +02:00
  • 0cdad37fff VexRiscvSmpClusterGen now implement ebreak Dolu1990 2021-07-11 21:55:33 +02:00
  • 91b3e79485 SpinalHDL version++ Dolu1990 2021-07-11 21:55:13 +02:00
  • a4c86130cc Update README.md Dolu1990 2021-07-08 09:47:54 +02:00
  • 9bc7dce857
         Update README.md Dolu1990 2021-07-08 09:47:54 +02:00
  • 28a75afe7a reduce regression time Dolu1990 2021-07-05 14:17:48 +02:00
  • c79357d1b2 VexRiscvSmpClusterGen no support atomic less configs Dolu1990 2021-07-05 12:38:54 +02:00
  • a380c3a36c Merge branch 'spinal_1.4.4' into dev Dolu1990 2021-07-05 11:37:53 +02:00
  • 551e76d244 VexRiscvSmpCluster add a few options spinal_1.4.4 Dolu1990 2021-07-02 19:04:30 +02:00
  • 3702ea03c0 Fix github actions Dolu1990 2021-06-23 11:48:53 +02:00
  • df7ac05db9 Update 2.13 compatibility Dolu1990 2021-06-23 11:48:38 +02:00
  • cdd8a7e94a add github action Dolu1990 2021-06-23 09:04:35 +02:00