mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-04-22 13:07:10 -04:00
3b0f2e9551
travis job naming reduce verilator cache size Fix dcache test timeout travis cleaning travis wip verilator wip fix java 10 compilation Travis wip travis rework
84 lines
1.7 KiB
YAML
84 lines
1.7 KiB
YAML
language: scala
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dist: xenial
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notifications:
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email:
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on_success: never
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scala:
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- 2.11.12
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sbt_args: -no-colors -J-Xss2m
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addons:
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apt:
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sources:
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- ubuntu-toolchain-r-test
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packages:
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- git
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- make
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- autoconf
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- g++
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- flex
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- bison
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jdk:
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- openjdk10
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jobs:
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include:
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- stage: prepare cache-verilator
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script:
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- cp scripts/regression/verilator.mk $HOME/makefile
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- cd $HOME
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- make verilator_binary
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- &test
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stage: Test
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name: TEST_DHRYSTONE
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script:
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- make regression_dhrystone -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_BAREMETAL
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script:
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- make regression_random_baremetal -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_BAREMETAL
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script:
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- make regression_random_baremetal -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_MIXED
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script:
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- make regression_random -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_LINUX
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script:
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- make regression_random_linux -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_LINUX
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script:
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- make regression_random_linux -C scripts/regression
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before_install:
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- cd ..
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- git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
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- cd VexRiscv
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- export VERILATOR_ROOT=$HOME/verilator
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- export PATH=$VERILATOR_ROOT/bin:$PATH
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before_cache:
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- rm -fv $HOME/.ivy2/.sbt.ivy.lock
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- find $HOME/.ivy2/cache -name "ivydata-*.properties" -print -delete
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- find $HOME/.sbt -name "*.lock" -print -delete
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cache:
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directories:
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- $HOME/.ivy2/cache
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- $HOME/.sbt
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- $HOME/verilator
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