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MADDR32/MSUBR32 (2 cycles)

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This commit is contained in:
Romain Dolbeau 2021-02-14 07:02:28 -05:00
parent 19ecba98c7
commit 06345f8ba0
3 changed files with 57 additions and 7 deletions
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48
data_Zpn_2cycles.txt
View file

@ -1,12 +1,17 @@
I SMAQA SMAQA 1100100----------000----01110111 pdpiumul8 Zpn I SMAQA SMAQA 1100100----------000----01110111 pdpimul8 Zpn
I UMAQA UMAQA 1100110----------000----01110111 pdpismul8 Zpn I UMAQA UMAQA 1100110----------000----01110111 pdpimul8 Zpn
I MADDR32 MADDR32 1100010----------000-----1110111 pdpimul32 Zpn
I MSUBR32 MSUBR32 1100011----------000-----1110111 pdpimul32 Zpn
S SMAQA "fun_smaqa1(input(SRC1), input(SRC2), input(SRC3))"
S SMAQA "fun_smaqa1(input(SRC1), input(SRC2), input(SRC3))" S UMAQA "fun_umaqa1(input(SRC1), input(SRC2), input(SRC3))"
S UMAQA "fun_umaqa1(input(SRC1), input(SRC2), input(SRC3))" T SMAQA 96 "fun_smaqa2"
T SMAQA 96 "fun_smaqa2" T UMAQA 96 "fun_umaqa2"
T UMAQA 96 "fun_umaqa2" S MADDR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
T MADDR32 128 "fun_maddr322"
S MSUBR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
T MSUBR32 128 "fun_msubr322"
P """ P """
def fun_smaqa1(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = { def fun_smaqa1(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
@ -43,4 +48,33 @@ P """
r.asBits.resize(32) // return value r.asBits.resize(32) // return value
} }
def fun_maddr321(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
val MUL_LL = rs1(15 downto 0).asUInt * rs2(15 downto 0).asUInt
val MUL_LH = rs1(15 downto 0).asUInt * rs2(31 downto 16).asUInt
val MUL_HL = rs1(31 downto 16).asUInt * rs2(15 downto 0).asUInt
rs3 ## MUL_HL ## MUL_LH ## MUL_LL // return value 128 bits
}
def fun_maddr322(input:Bits ) : Bits = {
val rs3 = input(127 downto 96)
val MUL_HL = input(95 downto 64)
val MUL_LH = input(63 downto 32)
val MUL_LL = input(31 downto 0)
val r = rs3.asUInt + MUL_LL.asUInt + (MUL_LH.asUInt << 16) + (MUL_HL.asUInt << 16)
r.asBits.resize(32) // return value
}
def fun_msubr322(input:Bits ) : Bits = {
val rs3 = input(127 downto 96)
val MUL_HL = input(95 downto 64)
val MUL_LH = input(63 downto 32)
val MUL_LL = input(31 downto 0)
val r = rs3.asUInt - MUL_LL.asUInt - (MUL_LH.asUInt << 16) - (MUL_HL.asUInt << 16)
r.asBits.resize(32) // return value
}
""" """

5
new_instructions_support_p.h
View file

@ -151,5 +151,10 @@ ASM3RMACRO(SMAQA, 0xc8000077)
FUN3R(__rv__smaqa, SMAQA) FUN3R(__rv__smaqa, SMAQA)
ASM3RMACRO(UMAQA, 0xcc000077) ASM3RMACRO(UMAQA, 0xcc000077)
FUN3R(__rv__umaqa, UMAQA) FUN3R(__rv__umaqa, UMAQA)
ASM3RMACRO(MADDR32, 0xc4000077)
FUN3R(__rv__maddr32, MADDR32)
ASM3RMACRO(MSUBR32, 0xc6000077)
FUN3R(__rv__msubr32, MSUBR32)
#endif // __NEW_INSTRUCTION_SUPPORT_P_H__ #endif // __NEW_INSTRUCTION_SUPPORT_P_H__

11
test_p.c
View file

@ -739,6 +739,14 @@ uint64_t __rv__umaqa(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3)
r = rs3 + c[0] + c[1] + c[2] + c[3]; r = rs3 + c[0] + c[1] + c[2] + c[3];
return r; return r;
} }
uint32_t __rv__maddr32(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3) {
return (rs1 * rs2) + rs3;
}
uint32_t __rv__msubr32(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3) {
return rs3 - (rs1 * rs2);
}
#endif // __riscv #endif // __riscv
unsigned int a = 0x01234567; unsigned int a = 0x01234567;
@ -897,6 +905,9 @@ int main(int argc, char **argv) {
T3(__rv__smaqa); T3(__rv__smaqa);
T3(__rv__umaqa); T3(__rv__umaqa);
T3(__rv__maddr32);
T3(__rv__msubr32);
b = 0x0100F004 + index; b = 0x0100F004 + index;
} }