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https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
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MADDR32/MSUBR32 (2 cycles)
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19ecba98c7
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3 changed files with 57 additions and 7 deletions
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@ -1,12 +1,17 @@
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I SMAQA SMAQA 1100100----------000----01110111 pdpiumul8 Zpn
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I UMAQA UMAQA 1100110----------000----01110111 pdpismul8 Zpn
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I SMAQA SMAQA 1100100----------000----01110111 pdpimul8 Zpn
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I UMAQA UMAQA 1100110----------000----01110111 pdpimul8 Zpn
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I MADDR32 MADDR32 1100010----------000-----1110111 pdpimul32 Zpn
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I MSUBR32 MSUBR32 1100011----------000-----1110111 pdpimul32 Zpn
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S SMAQA "fun_smaqa1(input(SRC1), input(SRC2), input(SRC3))"
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S UMAQA "fun_umaqa1(input(SRC1), input(SRC2), input(SRC3))"
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T SMAQA 96 "fun_smaqa2"
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T UMAQA 96 "fun_umaqa2"
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S SMAQA "fun_smaqa1(input(SRC1), input(SRC2), input(SRC3))"
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S UMAQA "fun_umaqa1(input(SRC1), input(SRC2), input(SRC3))"
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T SMAQA 96 "fun_smaqa2"
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T UMAQA 96 "fun_umaqa2"
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S MADDR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
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T MADDR32 128 "fun_maddr322"
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S MSUBR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
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T MSUBR32 128 "fun_msubr322"
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P """
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def fun_smaqa1(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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@ -43,4 +48,33 @@ P """
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r.asBits.resize(32) // return value
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}
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def fun_maddr321(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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val MUL_LL = rs1(15 downto 0).asUInt * rs2(15 downto 0).asUInt
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val MUL_LH = rs1(15 downto 0).asUInt * rs2(31 downto 16).asUInt
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val MUL_HL = rs1(31 downto 16).asUInt * rs2(15 downto 0).asUInt
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rs3 ## MUL_HL ## MUL_LH ## MUL_LL // return value 128 bits
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}
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def fun_maddr322(input:Bits ) : Bits = {
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val rs3 = input(127 downto 96)
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val MUL_HL = input(95 downto 64)
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val MUL_LH = input(63 downto 32)
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val MUL_LL = input(31 downto 0)
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val r = rs3.asUInt + MUL_LL.asUInt + (MUL_LH.asUInt << 16) + (MUL_HL.asUInt << 16)
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r.asBits.resize(32) // return value
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}
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def fun_msubr322(input:Bits ) : Bits = {
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val rs3 = input(127 downto 96)
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val MUL_HL = input(95 downto 64)
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val MUL_LH = input(63 downto 32)
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val MUL_LL = input(31 downto 0)
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val r = rs3.asUInt - MUL_LL.asUInt - (MUL_LH.asUInt << 16) - (MUL_HL.asUInt << 16)
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r.asBits.resize(32) // return value
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}
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"""
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@ -151,5 +151,10 @@ ASM3RMACRO(SMAQA, 0xc8000077)
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FUN3R(__rv__smaqa, SMAQA)
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ASM3RMACRO(UMAQA, 0xcc000077)
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FUN3R(__rv__umaqa, UMAQA)
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ASM3RMACRO(MADDR32, 0xc4000077)
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FUN3R(__rv__maddr32, MADDR32)
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ASM3RMACRO(MSUBR32, 0xc6000077)
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FUN3R(__rv__msubr32, MSUBR32)
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#endif // __NEW_INSTRUCTION_SUPPORT_P_H__
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11
test_p.c
11
test_p.c
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@ -739,6 +739,14 @@ uint64_t __rv__umaqa(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3)
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r = rs3 + c[0] + c[1] + c[2] + c[3];
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return r;
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}
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uint32_t __rv__maddr32(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3) {
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return (rs1 * rs2) + rs3;
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}
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uint32_t __rv__msubr32(const uint32_t rs1, const uint32_t rs2, const uint32_t rs3) {
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return rs3 - (rs1 * rs2);
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}
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#endif // __riscv
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unsigned int a = 0x01234567;
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T3(__rv__smaqa);
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T3(__rv__umaqa);
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T3(__rv__maddr32);
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T3(__rv__msubr32);
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b = 0x0100F004 + index;
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}
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