github-mirrors/VexRiscvBPluginGenerator
1
0
Fork 0
mirror of https://github.com/rdolbeau/VexRiscvBPluginGenerator.git synced 2025-04-18 18:44:42 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

move to K 0.9.0

Browse source
This commit is contained in:
Romain Dolbeau 2021-03-06 04:39:34 -05:00
parent e870f3ebe7
commit 25d43e10d3
5 changed files with 9 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
CryptoZkb.scala
View file

@ -17,7 +17,7 @@ object CryptoZkbPlugin {
val CTRL_XPERMdotB, CTRL_XPERMdotN = newElement()
}
object CryptoZkbCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
val CTRL_GORC, CTRL_REV8, CTRL_REVdotB = newElement()
val CTRL_REV8, CTRL_REVdotB = newElement()
}
object CryptoZkbCtrlshuffleEnum extends SpinalEnum(binarySequential) {
val CTRL_UNZIP, CTRL_ZIP = newElement()
@ -457,7 +457,6 @@ class CryptoZkbPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv]
def XPERMdotN_KEY = M"0010100----------010-----0110011"
def XPERMdotB_KEY = M"0010100----------100-----0110011"
def RORI_KEY = M"01100------------101-----0010011"
def GORCI_KEY = M"00101------------101-----0010011"
def REV8_KEY = M"011010011000-----101-----0010011"
def REVdotB_KEY = M"011010000111-----101-----0010011"
def ZIP_KEY = M"000010001111-----001-----0010011"
@ -476,7 +475,6 @@ class CryptoZkbPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv]
PACKH_KEY -> (binaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_pack, CryptoZkbCtrlpack -> CryptoZkbCtrlpackEnum.CTRL_PACKH)),
XPERMdotN_KEY -> (binaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_xperm, CryptoZkbCtrlxperm -> CryptoZkbCtrlxpermEnum.CTRL_XPERMdotN)),
XPERMdotB_KEY -> (binaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_xperm, CryptoZkbCtrlxperm -> CryptoZkbCtrlxpermEnum.CTRL_XPERMdotB)),
GORCI_KEY -> (immediateActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_grevorc, CryptoZkbCtrlgrevorc -> CryptoZkbCtrlgrevorcEnum.CTRL_GORC)),
REV8_KEY -> (unaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_grevorc, CryptoZkbCtrlgrevorc -> CryptoZkbCtrlgrevorcEnum.CTRL_REV8)),
REVdotB_KEY -> (unaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_grevorc, CryptoZkbCtrlgrevorc -> CryptoZkbCtrlgrevorcEnum.CTRL_REVdotB)),
ZIP_KEY -> (unaryActions ++ List(CryptoZkbCtrl -> CryptoZkbCtrlEnum.CTRL_shuffle, CryptoZkbCtrlshuffle -> CryptoZkbCtrlshuffleEnum.CTRL_ZIP)),
@ -507,7 +505,6 @@ class CryptoZkbPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv]
CryptoZkbCtrlxpermEnum.CTRL_XPERMdotN -> fun_xperm_n(input(SRC1), input(SRC2)).asBits
) // mux xperm
val val_grevorc = input(CryptoZkbCtrlgrevorc).mux(
CryptoZkbCtrlgrevorcEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
CryptoZkbCtrlgrevorcEnum.CTRL_REV8 -> fun_rev8(input(SRC1)).asBits,
CryptoZkbCtrlgrevorcEnum.CTRL_REVdotB -> fun_revdotb(input(SRC1)).asBits
) // mux grevorc

2
README.md
View file

@ -20,7 +20,7 @@ This has received limited testing in a [Linux-on-Litex-VexRiscv](https://github.
Also, the implementations of the instructions in SpinalHDL are written for tuncitonality, and not tuned or optimized in any way for performance/area/... (file usage.txt has some numbers).
A separate data file include prototype support for RV32Zkn[ed] (AES encryption/decryption instructions) and RV32Zknh (SHA hash instructions) from the [K ("crypto")](https://github.com/riscv/riscv-crypto) extension draft 0.8.1. This requires another patch to VexRiscv, as Zkn[ed] use field rs1 instead of rd for the output register. There is now support for SM3 and SM4 acceleration (collectively Zks), which requires an expanded version of the rs1-for-rd patch.
A separate data file include prototype support for RV32Zkn[ed] (AES encryption/decryption instructions) and RV32Zknh (SHA hash instructions) from the [K ("crypto")](https://github.com/riscv/riscv-crypto) extension draft 0.9.0. This requires another patch to VexRiscv, as Zkn[ed] use field rs1 instead of rd for the output register. There is now support for SM3 and SM4 acceleration (collectively Zks), which requires an expanded version of the rs1-for-rd patch.
There's also some experimental support for some [P ("packed SIMD")](https://github.com/riscv/riscv-p-spec) instructions. It requires even more patches to VexRiscv, first to use a third input sourced from the destination register (so not R4 format like B's ternaries), and second to enable Zp64 instructions that write to two registers (x(2n) and x(2n+1)).

6
data_bitmanip.txt
View file

@ -16,12 +16,12 @@
// Zbp:
// Zbs:
// Zba:
// Zbe: bcompress/bdecompress currently unimplemented
// Zbe: in a dedicated file for b[de]compress, 'data_bitmanip_compress.txt'
// Zbf:
// Zbc: in a dedicated file, 'data_clmul.txt'
// Zbm: ignored, RV64-only
// Zbr: ignored, crc32 unimplemented
// Zbt:
// Zbt: (requires three-operands patch to VexRiscv)
// B : should be Zbb, Zbp, Zbs, Zba, Zbe, Zbf, Zbc, Zbm
//
// INSTRUCTIONS
@ -91,7 +91,7 @@ I BCLRI BCLR 01001------------001-----0010011 singlebit Zbs
I BSETI BSET 00101------------001-----0010011 singlebit Zbs
I BINVI BINV 01101------------001-----0010011 singlebit Zbs
I BEXTI BEXT 01001------------101-----0010011 singlebit Zbs
I GORCI GORC 00101------------101-----0010011 grevorc Zbp Zkb
I GORCI GORC 00101------------101-----0010011 grevorc Zbp
I GREVI GREV 01101------------101-----0010011 grevorc Zbp
I SLLIdotUW SLLIdotUW 00001------------001-----0011011 SLLIdotUW
// register-immediate (6bits)

4
data_sm3.txt
View file

@ -1,5 +1,5 @@
I SM3P0 SM3P0 000100001000-----001-----0010011 sm3 Zks
I SM3P1 SM3P1 000100001001-----001-----0010011 sm3 Zks
I SM3P0 SM3P0 000100001000-----001-----0010011 sm3 Zks Zksh
I SM3P1 SM3P1 000100001001-----001-----0010011 sm3 Zks Zksh
S SM3P0 "fun_sm3p0(input(SRC1))"
S SM3P1 "fun_sm3p1(input(SRC1))"

4
data_sm4.txt
View file

@ -1,5 +1,5 @@
I SM4ED SM4ED --11000----------000000000110011 sm4 Zks
I SM4KS SM4KS --11010----------000000000110011 sm4 Zks
I SM4ED SM4ED --11000----------000000000110011 sm4 Zks Zksed
I SM4KS SM4KS --11010----------000000000110011 sm4 Zks Zksed
S SM4ED "fun_sm4ed(input(SRC1), input(SRC2), input(INSTRUCTION)(31 downto 30))"
S SM4KS "fun_sm4ks(input(SRC1), input(SRC2), input(INSTRUCTION)(31 downto 30))"