mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
drop patch, see the VexRiscv branch three_operands instead
This commit is contained in:
Romain Dolbeau
parent
cc4b44258c
commit
5a21dd7521
1 changed files with 0 additions and 238 deletions
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@ -1,238 +0,0 @@
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diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala
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index ee9be3d..c554429 100644
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--- a/src/main/scala/vexriscv/Riscv.scala
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+++ b/src/main/scala/vexriscv/Riscv.scala
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@@ -11,6 +11,7 @@ object Riscv{
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def funct3Range = 14 downto 12
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def rs1Range = 19 downto 15
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def rs2Range = 24 downto 20
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+ def rs3Range = 31 downto 27
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def csrRange = 31 downto 20
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case class IMM(instruction : Bits) extends Area{
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diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala
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index 5f7865c..7a64a74 100644
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--- a/src/main/scala/vexriscv/VexRiscv.scala
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+++ b/src/main/scala/vexriscv/VexRiscv.scala
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@@ -36,8 +36,10 @@ case class VexRiscvConfig(){
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object BYPASSABLE_MEMORY_STAGE extends Stageable(Bool)
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object RS1 extends Stageable(Bits(32 bits))
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object RS2 extends Stageable(Bits(32 bits))
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+ object RS3 extends Stageable(Bits(32 bits))
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object RS1_USE extends Stageable(Bool)
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object RS2_USE extends Stageable(Bool)
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+ object RS3_USE extends Stageable(Bool)
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object RESULT extends Stageable(UInt(32 bits))
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object PC extends Stageable(UInt(32 bits))
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object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits))
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@@ -52,6 +54,7 @@ case class VexRiscvConfig(){
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object SRC1 extends Stageable(Bits(32 bits))
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object SRC2 extends Stageable(Bits(32 bits))
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+ object SRC3 extends Stageable(Bits(32 bits))
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object SRC_ADD_SUB extends Stageable(Bits(32 bits))
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object SRC_ADD extends Stageable(Bits(32 bits))
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object SRC_SUB extends Stageable(Bits(32 bits))
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@@ -81,8 +84,13 @@ case class VexRiscvConfig(){
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object Src2CtrlEnum extends SpinalEnum(binarySequential){
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val RS, IMI, IMS, PC = newElement() //TODO remplacing ZERO could avoid 32 muxes if SRC_ADD can be disabled
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}
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+
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+ object Src3CtrlEnum extends SpinalEnum(binarySequential){
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+ val RS, IMI = newElement()
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+ }
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object SRC1_CTRL extends Stageable(Src1CtrlEnum())
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object SRC2_CTRL extends Stageable(Src2CtrlEnum())
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+ object SRC3_CTRL extends Stageable(Src3CtrlEnum())
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}
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diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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index e01bd87..3966005 100644
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--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@@ -17,6 +17,7 @@ import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
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+import vexriscv.plugin._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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@@ -262,12 +263,17 @@ object VexRiscvSmpClusterGen {
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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- new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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+ //new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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+ new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY, mcycleAccess = CsrAccess.READ_ONLY, ucycleAccess = CsrAccess.READ_ONLY)),
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new BranchPlugin(
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earlyBranch = earlyBranch,
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catchAddressMisaligned = true,
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fenceiGenAsAJump = false
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),
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+ new BitManipAllPlugin,
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+ new BitManipZclmulPlugin,
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+ new CryptoZknePlugin,
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+ new CryptoZknhPlugin,
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new YamlPlugin(s"cpu$hartId.yaml")
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)
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)
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diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala
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index 1ed1d83..47d8bc1 100644
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--- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala
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+++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala
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@@ -33,6 +33,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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import pipeline.config._
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val src0Hazard = False
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val src1Hazard = False
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+ val src2Hazard = False
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val readStage = service(classOf[RegFileService]).readStage()
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@@ -40,6 +41,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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val runtimeBypassableValue = if(runtimeBypassable != null) stage.input(runtimeBypassable) else True
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val addr0Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs2Range)
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+ val addr2Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs3Range)
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when(stage.arbitration.isValid && stage.input(REGFILE_WRITE_VALID)) {
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if (bypassable) {
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when(runtimeBypassableValue) {
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@@ -49,6 +51,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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when(addr1Match) {
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readStage.input(RS2) := stage.output(REGFILE_WRITE_DATA)
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}
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+ when(addr2Match) {
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+ readStage.input(RS3) := stage.output(REGFILE_WRITE_DATA)
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+ }
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}
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}
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}
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@@ -60,6 +65,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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when(addr1Match) {
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src1Hazard := True
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}
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+ when(addr2Match) {
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+ src2Hazard := True
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+ }
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}
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}
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}
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@@ -76,6 +84,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs2Range)
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+ val addr2Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs3Range)
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when(writeBackBuffer.valid) {
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if (bypassWriteBackBuffer) {
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when(addr0Match) {
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@@ -84,6 +93,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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when(addr1Match) {
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readStage.input(RS2) := writeBackBuffer.data
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}
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+ when(addr2Match) {
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+ readStage.input(RS3) := writeBackBuffer.data
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+ }
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} else {
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when(addr0Match) {
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src0Hazard := True
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@@ -91,6 +103,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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when(addr1Match) {
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src1Hazard := True
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}
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+ when(addr2Match) {
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+ src2Hazard := True
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+ }
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}
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}
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@@ -106,9 +121,12 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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when(!readStage.input(RS2_USE)) {
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src1Hazard := False
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}
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+ when(!readStage.input(RS3_USE)) {
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+ src2Hazard := False
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+ }
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}
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- when(readStage.arbitration.isValid && (src0Hazard || src1Hazard)){
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+ when(readStage.arbitration.isValid && (src0Hazard || src1Hazard | src2Hazard)){
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readStage.arbitration.haltByOther := True
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}
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}
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diff --git a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala
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index 0520c2f..d99e5c2 100644
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--- a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala
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+++ b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala
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@@ -25,6 +25,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{
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val immediateActions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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+ SRC3_CTRL -> Src3CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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@@ -34,6 +35,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{
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val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.RS,
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+ SRC3_CTRL -> Src3CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
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index 0b7bcd2..834f836 100644
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--- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
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+++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
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@@ -29,6 +29,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(RS1_USE,False)
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decoderService.addDefault(RS2_USE,False)
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+ decoderService.addDefault(RS3_USE,False)
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decoderService.addDefault(REGFILE_WRITE_VALID,False)
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}
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@@ -74,16 +75,18 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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def shadowPrefix(that : Bits) = if(withShadow) global.shadow.read ## that else that
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val regFileReadAddress1 = U(shadowPrefix(srcInstruction(Riscv.rs1Range)))
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val regFileReadAddress2 = U(shadowPrefix(srcInstruction(Riscv.rs2Range)))
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+ val regFileReadAddress3 = U(shadowPrefix(srcInstruction(Riscv.rs3Range)))
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- val (rs1Data,rs2Data) = regFileReadyKind match{
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- case `ASYNC` => (global.regFile.readAsync(regFileReadAddress1),global.regFile.readAsync(regFileReadAddress2))
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+ val (rs1Data,rs2Data,rs3Data) = regFileReadyKind match{
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+ case `ASYNC` => (global.regFile.readAsync(regFileReadAddress1),global.regFile.readAsync(regFileReadAddress2),global.regFile.readAsync(regFileReadAddress3))
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case `SYNC` =>
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val enable = if(!syncUpdateOnStall) !readStage.arbitration.isStuck else null
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- (global.regFile.readSync(regFileReadAddress1, enable),global.regFile.readSync(regFileReadAddress2, enable))
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+ (global.regFile.readSync(regFileReadAddress1, enable),global.regFile.readSync(regFileReadAddress2, enable),global.regFile.readSync(regFileReadAddress3, enable))
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}
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insert(RS1) := rs1Data
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insert(RS2) := rs2Data
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+ insert(RS3) := rs3Data
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}
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//Write register file
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@@ -112,4 +115,4 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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}
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}
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}
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-}
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\ No newline at end of file
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+}
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diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala
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index eb5ab1f..24aab5c 100644
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--- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala
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+++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala
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@@ -39,6 +39,10 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean =
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Src2CtrlEnum.IMS -> imm.s_sext.resized,
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Src2CtrlEnum.PC -> output(PC).asBits
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)
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+ insert(SRC3) := input(SRC3_CTRL).mux(
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+ Src3CtrlEnum.RS -> output(RS3),
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+ Src2CtrlEnum.IMI -> imm.i_sext.resized
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+ )
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}
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val addSubStage = if(decodeAddSub) decode else execute
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