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update README, Makefile comments

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Romain Dolbeau 2021-02-16 13:11:15 -05:00
parent 051a96c2fa
commit 5e536f3f75
2 changed files with 5 additions and 2 deletions
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5
Makefile
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@ -88,7 +88,8 @@ CryptoZkb.scala: gen_plugin data_bitmanip.txt data_bitmanip_ZbbOnly.txt
CryptoZkg.scala: gen_plugin data_clmul.txt
./gen_plugin -n CryptoZkg -i data_clmul.txt -I CLMUL -I CLMULH >| $@
## Full Zkn not there yet, missing Zknd (AES decode)
## Full Zkn is Zknd + Zkne + Zknh + Zkg + Zkb
## For Zkb, beware the overlap with a lot of B plugins
CryptoZknd.scala: gen_plugin data_aes.txt
./gen_plugin -n CryptoZknd -i data_aes.txt -I Zknd >| $@
@ -99,6 +100,8 @@ CryptoZkne.scala: gen_plugin data_aes.txt
CryptoZknh.scala: gen_plugin data_sha.txt
./gen_plugin -n CryptoZknh -i data_sha.txt -I '*' >| $@
## Zks, Zkr not supported
PDataProcess.scala: gen_plugin data_Zpn.txt
./gen_plugin -n PDataProcess -i data_Zpn.txt -I Zpn >| $@

2
README.md
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@ -21,7 +21,7 @@ This has received limited testing in a [Linux-on-Litex-VexRiscv](https://github.
Also, the implementations of the instructions in SpinalHDL are written for tuncitonality, and not tuned or optimized in any way for performance/area/... (file usage.txt has some numbers).
A separate data file include prototype support for RV32Zkne (AES encryption instructions) and RV32Zknh (SHA hash instructions) from the [K ("crypto")](https://github.com/riscv/riscv-crypto) extension draft 0.8.1. This requires another patch to VexRiscv, as Zkne uses field rs1 instead of rd for the output register.
A separate data file include prototype support for RV32Zkn[ed] (AES encryption/decryption instructions) and RV32Zknh (SHA hash instructions) from the [K ("crypto")](https://github.com/riscv/riscv-crypto) extension draft 0.8.1. This requires another patch to VexRiscv, as Zkn[ed] use field rs1 instead of rd for the output register.
There's also some experimental support for some [P ("packed SIMD")](https://github.com/riscv/riscv-p-spec) instructions. It requires even more patches to VexRiscv, first to use a third input sourced from the destination register (so not R4 format like B's ternaries), and second to enable Zp64 instructions that write to two registers (x(2n) and x(2n+1)).