mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-16 09:44:41 -04:00
add specialized versions of instructions in their own file for Zbb, proper definition of various Zb* plugins
This commit is contained in:
Romain Dolbeau
parent
835321ae87
commit
901122bd12
11 changed files with 2438 additions and 119 deletions
417
BitManipZba.scala
Normal file
417
BitManipZba.scala
Normal file
|
|
@ -0,0 +1,417 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbaPlugin {
|
||||
object BitManipZbaCtrlsh_addEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SH1ADD, CTRL_SH2ADD, CTRL_SH3ADD = newElement()
|
||||
}
|
||||
object BitManipZbaCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_sh_add = newElement()
|
||||
}
|
||||
object BitManipZbaCtrlsh_add extends Stageable(BitManipZbaCtrlsh_addEnum())
|
||||
object BitManipZbaCtrl extends Stageable(BitManipZbaCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
def fun_grev( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized OR-combine
|
||||
def fun_gorc( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
|
||||
// helper function for the implementation of the generalized shuffles
|
||||
def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
|
||||
val x = src & ~(maskL | maskR)
|
||||
val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
|
||||
x2 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized shuffle
|
||||
def fun_shfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
|
||||
val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
|
||||
val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
|
||||
val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized unshuffle
|
||||
def fun_unshfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
|
||||
val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
|
||||
val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
|
||||
// this is trying to look like DOI 10.2478/jee-2015-0054
|
||||
def fun_clz_NLCi(x:Bits): Bits = {
|
||||
val r2 = (~(x(0) | x(1) | x(2) | x(3)))
|
||||
val r1 = (~(x(2) | x(3)))
|
||||
val r0 = (~(x(3) | (x(1) & ~x(2))))
|
||||
val r = r2 ## r1 ## r0
|
||||
r // return value
|
||||
}
|
||||
def fun_clz_BNE(a:Bits) : Bits = {
|
||||
val a01 = ~(a(0) & a(1))
|
||||
val a23 = ~(a(2) & a(3))
|
||||
|
||||
val a45 = ~(a(4) & a(5))
|
||||
val a67 = ~(a(6) & a(7))
|
||||
|
||||
val a0123 = ~(a01 | a23) // also r(2)
|
||||
val a4567 = ~(a45 | a67)
|
||||
|
||||
val a56 = ~(a(5) & ~a(6))
|
||||
val a024 = (a(0) & a(2) & a(4)) // AND not NAND
|
||||
val a13 = ~(a(1) & a(3))
|
||||
val a12 = ~(a(1) & ~a(2))
|
||||
|
||||
val r3 = ((a0123 & a4567)) // AND not NAND
|
||||
val r2 = (a0123)
|
||||
val r1 = (~(a01 | (~a23 & a45)))
|
||||
val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
|
||||
|
||||
val r = r3 ## r2 ## r1 ##r0
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_clz(in:Bits) : Bits = {
|
||||
val nlc7 = fun_clz_NLCi(in(31 downto 28))
|
||||
val nlc6 = fun_clz_NLCi(in(27 downto 24))
|
||||
val nlc5 = fun_clz_NLCi(in(23 downto 20))
|
||||
val nlc4 = fun_clz_NLCi(in(19 downto 16))
|
||||
val nlc3 = fun_clz_NLCi(in(15 downto 12))
|
||||
val nlc2 = fun_clz_NLCi(in(11 downto 8))
|
||||
val nlc1 = fun_clz_NLCi(in( 7 downto 4))
|
||||
val nlc0 = fun_clz_NLCi(in( 3 downto 0))
|
||||
val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
|
||||
val bne = fun_clz_BNE(a)
|
||||
|
||||
val muxo = (bne(2 downto 0)).mux(
|
||||
B"3'b000" -> nlc7(1 downto 0),
|
||||
B"3'b001" -> nlc6(1 downto 0),
|
||||
B"3'b010" -> nlc5(1 downto 0),
|
||||
B"3'b011" -> nlc4(1 downto 0),
|
||||
B"3'b100" -> nlc3(1 downto 0),
|
||||
B"3'b101" -> nlc2(1 downto 0),
|
||||
B"3'b110" -> nlc1(1 downto 0),
|
||||
B"3'b111" -> nlc0(1 downto 0)
|
||||
)
|
||||
val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
|
||||
|
||||
r.resize(32) // return value
|
||||
}
|
||||
// For trailing count, count using use leading count on bit-reversed value
|
||||
def fun_ctz(in:Bits) : Bits = {
|
||||
val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
|
||||
fun_clz(inr) // return value
|
||||
}
|
||||
|
||||
// naive popcnt
|
||||
def fun_popcnt(in:Bits) : Bits = {
|
||||
val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
|
||||
in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
|
||||
in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
|
||||
in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
|
||||
in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
|
||||
in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
|
||||
in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
|
||||
in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
//XPERMs
|
||||
def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(3 downto 0).asUInt
|
||||
val i1 = rs2(7 downto 4).asUInt
|
||||
val i2 = rs2(11 downto 8).asUInt
|
||||
val i3 = rs2(15 downto 12).asUInt
|
||||
val i4 = rs2(19 downto 16).asUInt
|
||||
val i5 = rs2(23 downto 20).asUInt
|
||||
val i6 = rs2(27 downto 24).asUInt
|
||||
val i7 = rs2(31 downto 28).asUInt
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r4 = (i4).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r5 = (i5).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r6 = (i6).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r7 = (i7).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(7 downto 0).asUInt;
|
||||
val i1 = rs2(15 downto 8).asUInt;
|
||||
val i2 = rs2(23 downto 16).asUInt;
|
||||
val i3 = rs2(31 downto 24).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(15 downto 0).asUInt;
|
||||
val i1 = rs2(31 downto 16).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
r1 ## r0 // return value
|
||||
}
|
||||
|
||||
def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbaPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbaPlugin._
|
||||
object IS_BitManipZba extends Stageable(Bool)
|
||||
object BitManipZba_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZba -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZba -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZba -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZba -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZba -> True
|
||||
)
|
||||
def SH1ADD_KEY = M"0010000----------010-----0110011"
|
||||
def SH2ADD_KEY = M"0010000----------100-----0110011"
|
||||
def SH3ADD_KEY = M"0010000----------110-----0110011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZba, False)
|
||||
decoderService.add(List(
|
||||
SH1ADD_KEY -> (binaryActions ++ List(BitManipZbaCtrl -> BitManipZbaCtrlEnum.CTRL_sh_add, BitManipZbaCtrlsh_add -> BitManipZbaCtrlsh_addEnum.CTRL_SH1ADD)),
|
||||
SH2ADD_KEY -> (binaryActions ++ List(BitManipZbaCtrl -> BitManipZbaCtrlEnum.CTRL_sh_add, BitManipZbaCtrlsh_add -> BitManipZbaCtrlsh_addEnum.CTRL_SH2ADD)),
|
||||
SH3ADD_KEY -> (binaryActions ++ List(BitManipZbaCtrl -> BitManipZbaCtrlEnum.CTRL_sh_add, BitManipZbaCtrlsh_add -> BitManipZbaCtrlsh_addEnum.CTRL_SH3ADD))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_sh_add = input(BitManipZbaCtrlsh_add).mux(
|
||||
BitManipZbaCtrlsh_addEnum.CTRL_SH1ADD -> ((input(SRC1) |<< 1).asUInt + input(SRC2).asUInt).asBits,
|
||||
BitManipZbaCtrlsh_addEnum.CTRL_SH2ADD -> ((input(SRC1) |<< 2).asUInt + input(SRC2).asUInt).asBits,
|
||||
BitManipZbaCtrlsh_addEnum.CTRL_SH3ADD -> ((input(SRC1) |<< 3).asUInt + input(SRC2).asUInt).asBits
|
||||
) // mux sh_add
|
||||
insert(BitManipZba_FINAL_OUTPUT) := val_sh_add.asBits
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZba)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZba_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
|
|
@ -3,39 +3,35 @@
|
|||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbpPlugin {
|
||||
object BitManipZbpCtrlbitwiseEnum extends SpinalEnum(binarySequential) {
|
||||
object BitManipZbbPlugin {
|
||||
object BitManipZbbCtrlbitwiseEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ANDN, CTRL_ORN, CTRL_XNOR = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlrotationEnum extends SpinalEnum(binarySequential) {
|
||||
object BitManipZbbCtrlrotationEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ROL, CTRL_ROR = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlgrevrocEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_GORC, CTRL_GREV = newElement()
|
||||
object BitManipZbbCtrlminmaxEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_MAX, CTRL_MAXU, CTRL_MIN, CTRL_MINU = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlshuffleEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SHFL, CTRL_UNSHFL = newElement()
|
||||
object BitManipZbbCtrlcountzeroesEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_CLZ, CTRL_CPOP, CTRL_CTZ = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlpackEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_PACK, CTRL_PACKH, CTRL_PACKU = newElement()
|
||||
object BitManipZbbCtrlsignextendEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SEXTdotB, CTRL_SEXTdotH, CTRL_ZEXTdotH = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlxpermEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_XPERMdotB, CTRL_XPERMdotH, CTRL_XPERMdotN = newElement()
|
||||
object BitManipZbbCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ORCdotB, CTRL_REV8 = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_GORC, CTRL_GREV = newElement()
|
||||
object BitManipZbbCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_bitwise, CTRL_rotation, CTRL_minmax, CTRL_countzeroes, CTRL_signextend, CTRL_grevorc = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_bitwise, CTRL_rotation, CTRL_grevroc, CTRL_shuffle, CTRL_pack, CTRL_xperm, CTRL_grevorc = newElement()
|
||||
}
|
||||
object BitManipZbpCtrlbitwise extends Stageable(BitManipZbpCtrlbitwiseEnum())
|
||||
object BitManipZbpCtrlrotation extends Stageable(BitManipZbpCtrlrotationEnum())
|
||||
object BitManipZbpCtrlgrevroc extends Stageable(BitManipZbpCtrlgrevrocEnum())
|
||||
object BitManipZbpCtrlshuffle extends Stageable(BitManipZbpCtrlshuffleEnum())
|
||||
object BitManipZbpCtrlpack extends Stageable(BitManipZbpCtrlpackEnum())
|
||||
object BitManipZbpCtrlxperm extends Stageable(BitManipZbpCtrlxpermEnum())
|
||||
object BitManipZbpCtrlgrevorc extends Stageable(BitManipZbpCtrlgrevorcEnum())
|
||||
object BitManipZbpCtrl extends Stageable(BitManipZbpCtrlEnum())
|
||||
object BitManipZbbCtrlbitwise extends Stageable(BitManipZbbCtrlbitwiseEnum())
|
||||
object BitManipZbbCtrlrotation extends Stageable(BitManipZbbCtrlrotationEnum())
|
||||
object BitManipZbbCtrlminmax extends Stageable(BitManipZbbCtrlminmaxEnum())
|
||||
object BitManipZbbCtrlcountzeroes extends Stageable(BitManipZbbCtrlcountzeroesEnum())
|
||||
object BitManipZbbCtrlsignextend extends Stageable(BitManipZbbCtrlsignextendEnum())
|
||||
object BitManipZbbCtrlgrevorc extends Stageable(BitManipZbbCtrlgrevorcEnum())
|
||||
object BitManipZbbCtrl extends Stageable(BitManipZbbCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
|
|
@ -349,12 +345,26 @@ object BitManipZbpPlugin {
|
|||
r // return value
|
||||
}
|
||||
|
||||
|
||||
def fun_rev8(a:Bits) : Bits = {
|
||||
val r = a(7 downto 0) ## a(15 downto 8) ## a(23 downto 16) ## a(31 downto 24)
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_orcb(a:Bits) : Bits = {
|
||||
val x1 = (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1))
|
||||
val x2 = (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2))
|
||||
val x4 = (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4))
|
||||
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbpPlugin._
|
||||
object IS_BitManipZbp extends Stageable(Bool)
|
||||
object BitManipZbp_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
class BitManipZbbPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbbPlugin._
|
||||
object IS_BitManipZbb extends Stageable(Bool)
|
||||
object BitManipZbb_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
|
|
@ -364,7 +374,7 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbp -> True
|
||||
IS_BitManipZbb -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
|
|
@ -374,7 +384,7 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZbp -> True
|
||||
IS_BitManipZbb -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
|
|
@ -382,7 +392,7 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbp -> True
|
||||
IS_BitManipZbb -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
|
|
@ -394,7 +404,7 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbp -> True
|
||||
IS_BitManipZbb -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
|
|
@ -405,51 +415,47 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbp -> True
|
||||
IS_BitManipZbb -> True
|
||||
)
|
||||
def ANDN_KEY = M"0100000----------111-----0110011"
|
||||
def ORN_KEY = M"0100000----------110-----0110011"
|
||||
def XNOR_KEY = M"0100000----------100-----0110011"
|
||||
def ROL_KEY = M"0110000----------001-----0110011"
|
||||
def ROR_KEY = M"0110000----------101-----0110011"
|
||||
def GORC_KEY = M"0010100----------101-----0110011"
|
||||
def GREV_KEY = M"0110100----------101-----0110011"
|
||||
def SHFL_KEY = M"0000100----------001-----0110011"
|
||||
def UNSHFL_KEY = M"0000100----------101-----0110011"
|
||||
def PACK_KEY = M"0000100----------100-----0110011"
|
||||
def PACKU_KEY = M"0100100----------100-----0110011"
|
||||
def PACKH_KEY = M"0000100----------111-----0110011"
|
||||
def XPERMdotN_KEY = M"0010100----------010-----0110011"
|
||||
def XPERMdotB_KEY = M"0010100----------100-----0110011"
|
||||
def XPERMdotH_KEY = M"0010100----------110-----0110011"
|
||||
def MIN_KEY = M"0000101----------100-----0110011"
|
||||
def MINU_KEY = M"0000101----------101-----0110011"
|
||||
def MAX_KEY = M"0000101----------110-----0110011"
|
||||
def MAXU_KEY = M"0000101----------111-----0110011"
|
||||
def RORI_KEY = M"01100------------101-----0010011"
|
||||
def GORCI_KEY = M"00101------------101-----0010011"
|
||||
def GREVI_KEY = M"01101------------101-----0010011"
|
||||
def SHFLI_KEY = M"000010-----------001-----0010011"
|
||||
def UNSHFLI_KEY = M"000010-----------101-----0010011"
|
||||
def CLZ_KEY = M"011000000000-----001-----0010011"
|
||||
def CTZ_KEY = M"011000000001-----001-----0010011"
|
||||
def CPOP_KEY = M"011000000010-----001-----0010011"
|
||||
def SEXTdotB_KEY = M"011000000100-----001-----0010011"
|
||||
def SEXTdotH_KEY = M"011000000101-----001-----0010011"
|
||||
def ZEXTdotH_KEY = M"000010000000-----100-----0110011"
|
||||
def ORCdotB_KEY = M"001010000111-----101-----0010011"
|
||||
def REV8_KEY = M"011010011000-----101-----0010011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZbp, False)
|
||||
decoderService.addDefault(IS_BitManipZbb, False)
|
||||
decoderService.add(List(
|
||||
ANDN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_ANDN)),
|
||||
ORN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_ORN)),
|
||||
XNOR_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_XNOR)),
|
||||
ROL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROL)),
|
||||
ROR_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROR)),
|
||||
RORI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROR)),
|
||||
GORC_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevroc, BitManipZbpCtrlgrevroc -> BitManipZbpCtrlgrevrocEnum.CTRL_GORC)),
|
||||
GREV_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevroc, BitManipZbpCtrlgrevroc -> BitManipZbpCtrlgrevrocEnum.CTRL_GREV)),
|
||||
SHFL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_SHFL)),
|
||||
UNSHFL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
||||
SHFLI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_SHFL)),
|
||||
UNSHFLI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
||||
PACK_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACK)),
|
||||
PACKU_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACKU)),
|
||||
PACKH_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACKH)),
|
||||
XPERMdotN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotN)),
|
||||
XPERMdotB_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotB)),
|
||||
XPERMdotH_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotH)),
|
||||
GORCI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevorc, BitManipZbpCtrlgrevorc -> BitManipZbpCtrlgrevorcEnum.CTRL_GORC)),
|
||||
GREVI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevorc, BitManipZbpCtrlgrevorc -> BitManipZbpCtrlgrevorcEnum.CTRL_GREV))
|
||||
ANDN_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_bitwise, BitManipZbbCtrlbitwise -> BitManipZbbCtrlbitwiseEnum.CTRL_ANDN)),
|
||||
ORN_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_bitwise, BitManipZbbCtrlbitwise -> BitManipZbbCtrlbitwiseEnum.CTRL_ORN)),
|
||||
XNOR_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_bitwise, BitManipZbbCtrlbitwise -> BitManipZbbCtrlbitwiseEnum.CTRL_XNOR)),
|
||||
ROL_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_rotation, BitManipZbbCtrlrotation -> BitManipZbbCtrlrotationEnum.CTRL_ROL)),
|
||||
ROR_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_rotation, BitManipZbbCtrlrotation -> BitManipZbbCtrlrotationEnum.CTRL_ROR)),
|
||||
RORI_KEY -> (immediateActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_rotation, BitManipZbbCtrlrotation -> BitManipZbbCtrlrotationEnum.CTRL_ROR)),
|
||||
MIN_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_minmax, BitManipZbbCtrlminmax -> BitManipZbbCtrlminmaxEnum.CTRL_MIN)),
|
||||
MINU_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_minmax, BitManipZbbCtrlminmax -> BitManipZbbCtrlminmaxEnum.CTRL_MINU)),
|
||||
MAX_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_minmax, BitManipZbbCtrlminmax -> BitManipZbbCtrlminmaxEnum.CTRL_MAX)),
|
||||
MAXU_KEY -> (binaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_minmax, BitManipZbbCtrlminmax -> BitManipZbbCtrlminmaxEnum.CTRL_MAXU)),
|
||||
CLZ_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_countzeroes, BitManipZbbCtrlcountzeroes -> BitManipZbbCtrlcountzeroesEnum.CTRL_CLZ)),
|
||||
CTZ_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_countzeroes, BitManipZbbCtrlcountzeroes -> BitManipZbbCtrlcountzeroesEnum.CTRL_CTZ)),
|
||||
CPOP_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_countzeroes, BitManipZbbCtrlcountzeroes -> BitManipZbbCtrlcountzeroesEnum.CTRL_CPOP)),
|
||||
SEXTdotB_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_signextend, BitManipZbbCtrlsignextend -> BitManipZbbCtrlsignextendEnum.CTRL_SEXTdotB)),
|
||||
SEXTdotH_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_signextend, BitManipZbbCtrlsignextend -> BitManipZbbCtrlsignextendEnum.CTRL_SEXTdotH)),
|
||||
ZEXTdotH_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_signextend, BitManipZbbCtrlsignextend -> BitManipZbbCtrlsignextendEnum.CTRL_ZEXTdotH)),
|
||||
ORCdotB_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_grevorc, BitManipZbbCtrlgrevorc -> BitManipZbbCtrlgrevorcEnum.CTRL_ORCdotB)),
|
||||
REV8_KEY -> (unaryActions ++ List(BitManipZbbCtrl -> BitManipZbbCtrlEnum.CTRL_grevorc, BitManipZbbCtrlgrevorc -> BitManipZbbCtrlgrevorcEnum.CTRL_REV8))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
|
|
@ -457,52 +463,49 @@ class BitManipZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv
|
|||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_bitwise = input(BitManipZbpCtrlbitwise).mux(
|
||||
BitManipZbpCtrlbitwiseEnum.CTRL_ANDN -> (input(SRC1) & ~input(SRC2)).asBits,
|
||||
BitManipZbpCtrlbitwiseEnum.CTRL_ORN -> (input(SRC1) | ~input(SRC2)).asBits,
|
||||
BitManipZbpCtrlbitwiseEnum.CTRL_XNOR -> (input(SRC1) ^ ~input(SRC2)).asBits
|
||||
val val_bitwise = input(BitManipZbbCtrlbitwise).mux(
|
||||
BitManipZbbCtrlbitwiseEnum.CTRL_ANDN -> (input(SRC1) & ~input(SRC2)).asBits,
|
||||
BitManipZbbCtrlbitwiseEnum.CTRL_ORN -> (input(SRC1) | ~input(SRC2)).asBits,
|
||||
BitManipZbbCtrlbitwiseEnum.CTRL_XNOR -> (input(SRC1) ^ ~input(SRC2)).asBits
|
||||
) // mux bitwise
|
||||
val val_rotation = input(BitManipZbpCtrlrotation).mux(
|
||||
BitManipZbpCtrlrotationEnum.CTRL_ROL -> input(SRC1).rotateLeft((input(SRC2)&31)(4 downto 0).asUInt).asBits,
|
||||
BitManipZbpCtrlrotationEnum.CTRL_ROR -> input(SRC1).rotateRight((input(SRC2)&31)(4 downto 0).asUInt).asBits
|
||||
val val_rotation = input(BitManipZbbCtrlrotation).mux(
|
||||
BitManipZbbCtrlrotationEnum.CTRL_ROL -> input(SRC1).rotateLeft((input(SRC2)&31)(4 downto 0).asUInt).asBits,
|
||||
BitManipZbbCtrlrotationEnum.CTRL_ROR -> input(SRC1).rotateRight((input(SRC2)&31)(4 downto 0).asUInt).asBits
|
||||
) // mux rotation
|
||||
val val_grevroc = input(BitManipZbpCtrlgrevroc).mux(
|
||||
BitManipZbpCtrlgrevrocEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbpCtrlgrevrocEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2)).asBits
|
||||
) // mux grevroc
|
||||
val val_shuffle = input(BitManipZbpCtrlshuffle).mux(
|
||||
BitManipZbpCtrlshuffleEnum.CTRL_SHFL -> fun_shfl32(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL -> fun_unshfl32(input(SRC1), input(SRC2)).asBits
|
||||
) // mux shuffle
|
||||
val val_pack = input(BitManipZbpCtrlpack).mux(
|
||||
BitManipZbpCtrlpackEnum.CTRL_PACK -> (input(SRC2)(15 downto 0) ## input(SRC1)(15 downto 0)).asBits,
|
||||
BitManipZbpCtrlpackEnum.CTRL_PACKH -> B"16'x0000" ## (input(SRC2)(7 downto 0) ## input(SRC1)(7 downto 0)).asBits,
|
||||
BitManipZbpCtrlpackEnum.CTRL_PACKU -> (input(SRC2)(31 downto 16) ## input(SRC1)(31 downto 16)).asBits
|
||||
) // mux pack
|
||||
val val_xperm = input(BitManipZbpCtrlxperm).mux(
|
||||
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotB -> fun_xperm_b(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotH -> fun_xperm_h(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotN -> fun_xperm_n(input(SRC1), input(SRC2)).asBits
|
||||
) // mux xperm
|
||||
val val_grevorc = input(BitManipZbpCtrlgrevorc).mux(
|
||||
BitManipZbpCtrlgrevorcEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbpCtrlgrevorcEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2)).asBits
|
||||
val val_minmax = input(BitManipZbbCtrlminmax).mux(
|
||||
BitManipZbbCtrlminmaxEnum.CTRL_MAX -> ((input(SRC1).asSInt > input(SRC2).asSInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbCtrlminmaxEnum.CTRL_MAXU -> ((input(SRC1).asUInt > input(SRC2).asUInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbCtrlminmaxEnum.CTRL_MIN -> ((input(SRC1).asSInt < input(SRC2).asSInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbCtrlminmaxEnum.CTRL_MINU -> ((input(SRC1).asUInt < input(SRC2).asUInt) ? input(SRC1) | input(SRC2)).asBits
|
||||
) // mux minmax
|
||||
val val_countzeroes = input(BitManipZbbCtrlcountzeroes).mux(
|
||||
BitManipZbbCtrlcountzeroesEnum.CTRL_CLZ -> fun_clz(input(SRC1)).asBits,
|
||||
BitManipZbbCtrlcountzeroesEnum.CTRL_CPOP -> fun_popcnt(input(SRC1)).asBits,
|
||||
BitManipZbbCtrlcountzeroesEnum.CTRL_CTZ -> fun_ctz(input(SRC1)).asBits
|
||||
) // mux countzeroes
|
||||
val val_signextend = input(BitManipZbbCtrlsignextend).mux(
|
||||
BitManipZbbCtrlsignextendEnum.CTRL_SEXTdotB -> (Bits(24 bits).setAllTo(input(SRC1)(7)) ## input(SRC1)(7 downto 0)).asBits,
|
||||
BitManipZbbCtrlsignextendEnum.CTRL_SEXTdotH -> (Bits(16 bits).setAllTo(input(SRC1)(15)) ## input(SRC1)(15 downto 0)).asBits,
|
||||
BitManipZbbCtrlsignextendEnum.CTRL_ZEXTdotH -> (B"16'x0000" ## input(SRC1)(15 downto 0)).asBits
|
||||
) // mux signextend
|
||||
val val_grevorc = input(BitManipZbbCtrlgrevorc).mux(
|
||||
BitManipZbbCtrlgrevorcEnum.CTRL_ORCdotB -> fun_orcb(input(SRC1)).asBits,
|
||||
BitManipZbbCtrlgrevorcEnum.CTRL_REV8 -> fun_rev8(input(SRC1)).asBits
|
||||
) // mux grevorc
|
||||
insert(BitManipZbp_FINAL_OUTPUT) := input(BitManipZbpCtrl).mux(
|
||||
BitManipZbpCtrlEnum.CTRL_bitwise -> val_bitwise.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_rotation -> val_rotation.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_grevroc -> val_grevroc.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_shuffle -> val_shuffle.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_pack -> val_pack.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_xperm -> val_xperm.asBits,
|
||||
BitManipZbpCtrlEnum.CTRL_grevorc -> val_grevorc.asBits
|
||||
insert(BitManipZbb_FINAL_OUTPUT) := input(BitManipZbbCtrl).mux(
|
||||
BitManipZbbCtrlEnum.CTRL_bitwise -> val_bitwise.asBits,
|
||||
BitManipZbbCtrlEnum.CTRL_rotation -> val_rotation.asBits,
|
||||
BitManipZbbCtrlEnum.CTRL_minmax -> val_minmax.asBits,
|
||||
BitManipZbbCtrlEnum.CTRL_countzeroes -> val_countzeroes.asBits,
|
||||
BitManipZbbCtrlEnum.CTRL_signextend -> val_signextend.asBits,
|
||||
BitManipZbbCtrlEnum.CTRL_grevorc -> val_grevorc.asBits
|
||||
) // primary mux
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZbp)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbp_FINAL_OUTPUT)
|
||||
when (arbitration.isValid && input(IS_BitManipZbb)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbb_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
557
BitManipZbbZbp.scala
Normal file
557
BitManipZbbZbp.scala
Normal file
|
|
@ -0,0 +1,557 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbbZbpPlugin {
|
||||
object BitManipZbbZbpCtrlbitwiseEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ANDN, CTRL_ORN, CTRL_XNOR = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlrotationEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ROL, CTRL_ROR = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlgrevrocEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_GORC, CTRL_GREV = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlminmaxEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_MAX, CTRL_MAXU, CTRL_MIN, CTRL_MINU = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlshuffleEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SHFL, CTRL_UNSHFL = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlpackEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_PACK, CTRL_PACKH, CTRL_PACKU = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlxpermEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_XPERMdotB, CTRL_XPERMdotH, CTRL_XPERMdotN = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_GORC, CTRL_GREV = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlcountzeroesEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_CLZ, CTRL_CPOP, CTRL_CTZ = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlsignextendEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SEXTdotB, CTRL_SEXTdotH = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_bitwise, CTRL_rotation, CTRL_grevroc, CTRL_minmax, CTRL_shuffle, CTRL_pack, CTRL_xperm, CTRL_grevorc, CTRL_countzeroes, CTRL_signextend = newElement()
|
||||
}
|
||||
object BitManipZbbZbpCtrlbitwise extends Stageable(BitManipZbbZbpCtrlbitwiseEnum())
|
||||
object BitManipZbbZbpCtrlrotation extends Stageable(BitManipZbbZbpCtrlrotationEnum())
|
||||
object BitManipZbbZbpCtrlgrevroc extends Stageable(BitManipZbbZbpCtrlgrevrocEnum())
|
||||
object BitManipZbbZbpCtrlminmax extends Stageable(BitManipZbbZbpCtrlminmaxEnum())
|
||||
object BitManipZbbZbpCtrlshuffle extends Stageable(BitManipZbbZbpCtrlshuffleEnum())
|
||||
object BitManipZbbZbpCtrlpack extends Stageable(BitManipZbbZbpCtrlpackEnum())
|
||||
object BitManipZbbZbpCtrlxperm extends Stageable(BitManipZbbZbpCtrlxpermEnum())
|
||||
object BitManipZbbZbpCtrlgrevorc extends Stageable(BitManipZbbZbpCtrlgrevorcEnum())
|
||||
object BitManipZbbZbpCtrlcountzeroes extends Stageable(BitManipZbbZbpCtrlcountzeroesEnum())
|
||||
object BitManipZbbZbpCtrlsignextend extends Stageable(BitManipZbbZbpCtrlsignextendEnum())
|
||||
object BitManipZbbZbpCtrl extends Stageable(BitManipZbbZbpCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
def fun_grev( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized OR-combine
|
||||
def fun_gorc( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
|
||||
// helper function for the implementation of the generalized shuffles
|
||||
def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
|
||||
val x = src & ~(maskL | maskR)
|
||||
val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
|
||||
x2 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized shuffle
|
||||
def fun_shfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
|
||||
val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
|
||||
val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
|
||||
val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized unshuffle
|
||||
def fun_unshfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
|
||||
val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
|
||||
val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
|
||||
// this is trying to look like DOI 10.2478/jee-2015-0054
|
||||
def fun_clz_NLCi(x:Bits): Bits = {
|
||||
val r2 = (~(x(0) | x(1) | x(2) | x(3)))
|
||||
val r1 = (~(x(2) | x(3)))
|
||||
val r0 = (~(x(3) | (x(1) & ~x(2))))
|
||||
val r = r2 ## r1 ## r0
|
||||
r // return value
|
||||
}
|
||||
def fun_clz_BNE(a:Bits) : Bits = {
|
||||
val a01 = ~(a(0) & a(1))
|
||||
val a23 = ~(a(2) & a(3))
|
||||
|
||||
val a45 = ~(a(4) & a(5))
|
||||
val a67 = ~(a(6) & a(7))
|
||||
|
||||
val a0123 = ~(a01 | a23) // also r(2)
|
||||
val a4567 = ~(a45 | a67)
|
||||
|
||||
val a56 = ~(a(5) & ~a(6))
|
||||
val a024 = (a(0) & a(2) & a(4)) // AND not NAND
|
||||
val a13 = ~(a(1) & a(3))
|
||||
val a12 = ~(a(1) & ~a(2))
|
||||
|
||||
val r3 = ((a0123 & a4567)) // AND not NAND
|
||||
val r2 = (a0123)
|
||||
val r1 = (~(a01 | (~a23 & a45)))
|
||||
val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
|
||||
|
||||
val r = r3 ## r2 ## r1 ##r0
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_clz(in:Bits) : Bits = {
|
||||
val nlc7 = fun_clz_NLCi(in(31 downto 28))
|
||||
val nlc6 = fun_clz_NLCi(in(27 downto 24))
|
||||
val nlc5 = fun_clz_NLCi(in(23 downto 20))
|
||||
val nlc4 = fun_clz_NLCi(in(19 downto 16))
|
||||
val nlc3 = fun_clz_NLCi(in(15 downto 12))
|
||||
val nlc2 = fun_clz_NLCi(in(11 downto 8))
|
||||
val nlc1 = fun_clz_NLCi(in( 7 downto 4))
|
||||
val nlc0 = fun_clz_NLCi(in( 3 downto 0))
|
||||
val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
|
||||
val bne = fun_clz_BNE(a)
|
||||
|
||||
val muxo = (bne(2 downto 0)).mux(
|
||||
B"3'b000" -> nlc7(1 downto 0),
|
||||
B"3'b001" -> nlc6(1 downto 0),
|
||||
B"3'b010" -> nlc5(1 downto 0),
|
||||
B"3'b011" -> nlc4(1 downto 0),
|
||||
B"3'b100" -> nlc3(1 downto 0),
|
||||
B"3'b101" -> nlc2(1 downto 0),
|
||||
B"3'b110" -> nlc1(1 downto 0),
|
||||
B"3'b111" -> nlc0(1 downto 0)
|
||||
)
|
||||
val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
|
||||
|
||||
r.resize(32) // return value
|
||||
}
|
||||
// For trailing count, count using use leading count on bit-reversed value
|
||||
def fun_ctz(in:Bits) : Bits = {
|
||||
val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
|
||||
fun_clz(inr) // return value
|
||||
}
|
||||
|
||||
// naive popcnt
|
||||
def fun_popcnt(in:Bits) : Bits = {
|
||||
val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
|
||||
in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
|
||||
in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
|
||||
in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
|
||||
in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
|
||||
in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
|
||||
in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
|
||||
in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
//XPERMs
|
||||
def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(3 downto 0).asUInt
|
||||
val i1 = rs2(7 downto 4).asUInt
|
||||
val i2 = rs2(11 downto 8).asUInt
|
||||
val i3 = rs2(15 downto 12).asUInt
|
||||
val i4 = rs2(19 downto 16).asUInt
|
||||
val i5 = rs2(23 downto 20).asUInt
|
||||
val i6 = rs2(27 downto 24).asUInt
|
||||
val i7 = rs2(31 downto 28).asUInt
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r4 = (i4).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r5 = (i5).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r6 = (i6).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r7 = (i7).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(7 downto 0).asUInt;
|
||||
val i1 = rs2(15 downto 8).asUInt;
|
||||
val i2 = rs2(23 downto 16).asUInt;
|
||||
val i3 = rs2(31 downto 24).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(15 downto 0).asUInt;
|
||||
val i1 = rs2(31 downto 16).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
r1 ## r0 // return value
|
||||
}
|
||||
|
||||
def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbbZbpPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbbZbpPlugin._
|
||||
object IS_BitManipZbbZbp extends Stageable(Bool)
|
||||
object BitManipZbbZbp_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbbZbp -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZbbZbp -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbbZbp -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbbZbp -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbbZbp -> True
|
||||
)
|
||||
def ANDN_KEY = M"0100000----------111-----0110011"
|
||||
def ORN_KEY = M"0100000----------110-----0110011"
|
||||
def XNOR_KEY = M"0100000----------100-----0110011"
|
||||
def ROL_KEY = M"0110000----------001-----0110011"
|
||||
def ROR_KEY = M"0110000----------101-----0110011"
|
||||
def GORC_KEY = M"0010100----------101-----0110011"
|
||||
def GREV_KEY = M"0110100----------101-----0110011"
|
||||
def MIN_KEY = M"0000101----------100-----0110011"
|
||||
def MINU_KEY = M"0000101----------101-----0110011"
|
||||
def MAX_KEY = M"0000101----------110-----0110011"
|
||||
def MAXU_KEY = M"0000101----------111-----0110011"
|
||||
def SHFL_KEY = M"0000100----------001-----0110011"
|
||||
def UNSHFL_KEY = M"0000100----------101-----0110011"
|
||||
def PACK_KEY = M"0000100----------100-----0110011"
|
||||
def PACKU_KEY = M"0100100----------100-----0110011"
|
||||
def PACKH_KEY = M"0000100----------111-----0110011"
|
||||
def XPERMdotN_KEY = M"0010100----------010-----0110011"
|
||||
def XPERMdotB_KEY = M"0010100----------100-----0110011"
|
||||
def XPERMdotH_KEY = M"0010100----------110-----0110011"
|
||||
def RORI_KEY = M"01100------------101-----0010011"
|
||||
def GORCI_KEY = M"00101------------101-----0010011"
|
||||
def GREVI_KEY = M"01101------------101-----0010011"
|
||||
def SHFLI_KEY = M"000010-----------001-----0010011"
|
||||
def UNSHFLI_KEY = M"000010-----------101-----0010011"
|
||||
def CLZ_KEY = M"011000000000-----001-----0010011"
|
||||
def CTZ_KEY = M"011000000001-----001-----0010011"
|
||||
def CPOP_KEY = M"011000000010-----001-----0010011"
|
||||
def SEXTdotB_KEY = M"011000000100-----001-----0010011"
|
||||
def SEXTdotH_KEY = M"011000000101-----001-----0010011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZbbZbp, False)
|
||||
decoderService.add(List(
|
||||
ANDN_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_bitwise, BitManipZbbZbpCtrlbitwise -> BitManipZbbZbpCtrlbitwiseEnum.CTRL_ANDN)),
|
||||
ORN_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_bitwise, BitManipZbbZbpCtrlbitwise -> BitManipZbbZbpCtrlbitwiseEnum.CTRL_ORN)),
|
||||
XNOR_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_bitwise, BitManipZbbZbpCtrlbitwise -> BitManipZbbZbpCtrlbitwiseEnum.CTRL_XNOR)),
|
||||
ROL_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_rotation, BitManipZbbZbpCtrlrotation -> BitManipZbbZbpCtrlrotationEnum.CTRL_ROL)),
|
||||
ROR_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_rotation, BitManipZbbZbpCtrlrotation -> BitManipZbbZbpCtrlrotationEnum.CTRL_ROR)),
|
||||
RORI_KEY -> (immediateActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_rotation, BitManipZbbZbpCtrlrotation -> BitManipZbbZbpCtrlrotationEnum.CTRL_ROR)),
|
||||
GORC_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_grevroc, BitManipZbbZbpCtrlgrevroc -> BitManipZbbZbpCtrlgrevrocEnum.CTRL_GORC)),
|
||||
GREV_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_grevroc, BitManipZbbZbpCtrlgrevroc -> BitManipZbbZbpCtrlgrevrocEnum.CTRL_GREV)),
|
||||
MIN_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_minmax, BitManipZbbZbpCtrlminmax -> BitManipZbbZbpCtrlminmaxEnum.CTRL_MIN)),
|
||||
MINU_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_minmax, BitManipZbbZbpCtrlminmax -> BitManipZbbZbpCtrlminmaxEnum.CTRL_MINU)),
|
||||
MAX_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_minmax, BitManipZbbZbpCtrlminmax -> BitManipZbbZbpCtrlminmaxEnum.CTRL_MAX)),
|
||||
MAXU_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_minmax, BitManipZbbZbpCtrlminmax -> BitManipZbbZbpCtrlminmaxEnum.CTRL_MAXU)),
|
||||
SHFL_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_shuffle, BitManipZbbZbpCtrlshuffle -> BitManipZbbZbpCtrlshuffleEnum.CTRL_SHFL)),
|
||||
UNSHFL_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_shuffle, BitManipZbbZbpCtrlshuffle -> BitManipZbbZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
||||
SHFLI_KEY -> (immediateActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_shuffle, BitManipZbbZbpCtrlshuffle -> BitManipZbbZbpCtrlshuffleEnum.CTRL_SHFL)),
|
||||
UNSHFLI_KEY -> (immediateActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_shuffle, BitManipZbbZbpCtrlshuffle -> BitManipZbbZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
||||
PACK_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_pack, BitManipZbbZbpCtrlpack -> BitManipZbbZbpCtrlpackEnum.CTRL_PACK)),
|
||||
PACKU_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_pack, BitManipZbbZbpCtrlpack -> BitManipZbbZbpCtrlpackEnum.CTRL_PACKU)),
|
||||
PACKH_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_pack, BitManipZbbZbpCtrlpack -> BitManipZbbZbpCtrlpackEnum.CTRL_PACKH)),
|
||||
XPERMdotN_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_xperm, BitManipZbbZbpCtrlxperm -> BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotN)),
|
||||
XPERMdotB_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_xperm, BitManipZbbZbpCtrlxperm -> BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotB)),
|
||||
XPERMdotH_KEY -> (binaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_xperm, BitManipZbbZbpCtrlxperm -> BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotH)),
|
||||
GORCI_KEY -> (immediateActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_grevorc, BitManipZbbZbpCtrlgrevorc -> BitManipZbbZbpCtrlgrevorcEnum.CTRL_GORC)),
|
||||
GREVI_KEY -> (immediateActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_grevorc, BitManipZbbZbpCtrlgrevorc -> BitManipZbbZbpCtrlgrevorcEnum.CTRL_GREV)),
|
||||
CLZ_KEY -> (unaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_countzeroes, BitManipZbbZbpCtrlcountzeroes -> BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CLZ)),
|
||||
CTZ_KEY -> (unaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_countzeroes, BitManipZbbZbpCtrlcountzeroes -> BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CTZ)),
|
||||
CPOP_KEY -> (unaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_countzeroes, BitManipZbbZbpCtrlcountzeroes -> BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CPOP)),
|
||||
SEXTdotB_KEY -> (unaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_signextend, BitManipZbbZbpCtrlsignextend -> BitManipZbbZbpCtrlsignextendEnum.CTRL_SEXTdotB)),
|
||||
SEXTdotH_KEY -> (unaryActions ++ List(BitManipZbbZbpCtrl -> BitManipZbbZbpCtrlEnum.CTRL_signextend, BitManipZbbZbpCtrlsignextend -> BitManipZbbZbpCtrlsignextendEnum.CTRL_SEXTdotH))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_bitwise = input(BitManipZbbZbpCtrlbitwise).mux(
|
||||
BitManipZbbZbpCtrlbitwiseEnum.CTRL_ANDN -> (input(SRC1) & ~input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlbitwiseEnum.CTRL_ORN -> (input(SRC1) | ~input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlbitwiseEnum.CTRL_XNOR -> (input(SRC1) ^ ~input(SRC2)).asBits
|
||||
) // mux bitwise
|
||||
val val_rotation = input(BitManipZbbZbpCtrlrotation).mux(
|
||||
BitManipZbbZbpCtrlrotationEnum.CTRL_ROL -> input(SRC1).rotateLeft((input(SRC2)&31)(4 downto 0).asUInt).asBits,
|
||||
BitManipZbbZbpCtrlrotationEnum.CTRL_ROR -> input(SRC1).rotateRight((input(SRC2)&31)(4 downto 0).asUInt).asBits
|
||||
) // mux rotation
|
||||
val val_grevroc = input(BitManipZbbZbpCtrlgrevroc).mux(
|
||||
BitManipZbbZbpCtrlgrevrocEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlgrevrocEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2)).asBits
|
||||
) // mux grevroc
|
||||
val val_minmax = input(BitManipZbbZbpCtrlminmax).mux(
|
||||
BitManipZbbZbpCtrlminmaxEnum.CTRL_MAX -> ((input(SRC1).asSInt > input(SRC2).asSInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlminmaxEnum.CTRL_MAXU -> ((input(SRC1).asUInt > input(SRC2).asUInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlminmaxEnum.CTRL_MIN -> ((input(SRC1).asSInt < input(SRC2).asSInt) ? input(SRC1) | input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlminmaxEnum.CTRL_MINU -> ((input(SRC1).asUInt < input(SRC2).asUInt) ? input(SRC1) | input(SRC2)).asBits
|
||||
) // mux minmax
|
||||
val val_shuffle = input(BitManipZbbZbpCtrlshuffle).mux(
|
||||
BitManipZbbZbpCtrlshuffleEnum.CTRL_SHFL -> fun_shfl32(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlshuffleEnum.CTRL_UNSHFL -> fun_unshfl32(input(SRC1), input(SRC2)).asBits
|
||||
) // mux shuffle
|
||||
val val_pack = input(BitManipZbbZbpCtrlpack).mux(
|
||||
BitManipZbbZbpCtrlpackEnum.CTRL_PACK -> (input(SRC2)(15 downto 0) ## input(SRC1)(15 downto 0)).asBits,
|
||||
BitManipZbbZbpCtrlpackEnum.CTRL_PACKH -> B"16'x0000" ## (input(SRC2)(7 downto 0) ## input(SRC1)(7 downto 0)).asBits,
|
||||
BitManipZbbZbpCtrlpackEnum.CTRL_PACKU -> (input(SRC2)(31 downto 16) ## input(SRC1)(31 downto 16)).asBits
|
||||
) // mux pack
|
||||
val val_xperm = input(BitManipZbbZbpCtrlxperm).mux(
|
||||
BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotB -> fun_xperm_b(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotH -> fun_xperm_h(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlxpermEnum.CTRL_XPERMdotN -> fun_xperm_n(input(SRC1), input(SRC2)).asBits
|
||||
) // mux xperm
|
||||
val val_grevorc = input(BitManipZbbZbpCtrlgrevorc).mux(
|
||||
BitManipZbbZbpCtrlgrevorcEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZbbZbpCtrlgrevorcEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2)).asBits
|
||||
) // mux grevorc
|
||||
val val_countzeroes = input(BitManipZbbZbpCtrlcountzeroes).mux(
|
||||
BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CLZ -> fun_clz(input(SRC1)).asBits,
|
||||
BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CPOP -> fun_popcnt(input(SRC1)).asBits,
|
||||
BitManipZbbZbpCtrlcountzeroesEnum.CTRL_CTZ -> fun_ctz(input(SRC1)).asBits
|
||||
) // mux countzeroes
|
||||
val val_signextend = input(BitManipZbbZbpCtrlsignextend).mux(
|
||||
BitManipZbbZbpCtrlsignextendEnum.CTRL_SEXTdotB -> (Bits(24 bits).setAllTo(input(SRC1)(7)) ## input(SRC1)(7 downto 0)).asBits,
|
||||
BitManipZbbZbpCtrlsignextendEnum.CTRL_SEXTdotH -> (Bits(16 bits).setAllTo(input(SRC1)(15)) ## input(SRC1)(15 downto 0)).asBits
|
||||
) // mux signextend
|
||||
insert(BitManipZbbZbp_FINAL_OUTPUT) := input(BitManipZbbZbpCtrl).mux(
|
||||
BitManipZbbZbpCtrlEnum.CTRL_bitwise -> val_bitwise.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_rotation -> val_rotation.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_grevroc -> val_grevroc.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_minmax -> val_minmax.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_shuffle -> val_shuffle.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_pack -> val_pack.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_xperm -> val_xperm.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_grevorc -> val_grevorc.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_countzeroes -> val_countzeroes.asBits,
|
||||
BitManipZbbZbpCtrlEnum.CTRL_signextend -> val_signextend.asBits
|
||||
) // primary mux
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZbbZbp)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbbZbp_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
419
BitManipZbf.scala
Normal file
419
BitManipZbf.scala
Normal file
|
|
@ -0,0 +1,419 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbfPlugin {
|
||||
object BitManipZbfCtrlpackEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_PACK, CTRL_PACKH = newElement()
|
||||
}
|
||||
object BitManipZbfCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_pack, CTRL_BFP = newElement()
|
||||
}
|
||||
object BitManipZbfCtrlpack extends Stageable(BitManipZbfCtrlpackEnum())
|
||||
object BitManipZbfCtrl extends Stageable(BitManipZbfCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
def fun_grev( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized OR-combine
|
||||
def fun_gorc( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
|
||||
// helper function for the implementation of the generalized shuffles
|
||||
def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
|
||||
val x = src & ~(maskL | maskR)
|
||||
val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
|
||||
x2 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized shuffle
|
||||
def fun_shfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
|
||||
val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
|
||||
val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
|
||||
val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized unshuffle
|
||||
def fun_unshfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
|
||||
val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
|
||||
val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
|
||||
// this is trying to look like DOI 10.2478/jee-2015-0054
|
||||
def fun_clz_NLCi(x:Bits): Bits = {
|
||||
val r2 = (~(x(0) | x(1) | x(2) | x(3)))
|
||||
val r1 = (~(x(2) | x(3)))
|
||||
val r0 = (~(x(3) | (x(1) & ~x(2))))
|
||||
val r = r2 ## r1 ## r0
|
||||
r // return value
|
||||
}
|
||||
def fun_clz_BNE(a:Bits) : Bits = {
|
||||
val a01 = ~(a(0) & a(1))
|
||||
val a23 = ~(a(2) & a(3))
|
||||
|
||||
val a45 = ~(a(4) & a(5))
|
||||
val a67 = ~(a(6) & a(7))
|
||||
|
||||
val a0123 = ~(a01 | a23) // also r(2)
|
||||
val a4567 = ~(a45 | a67)
|
||||
|
||||
val a56 = ~(a(5) & ~a(6))
|
||||
val a024 = (a(0) & a(2) & a(4)) // AND not NAND
|
||||
val a13 = ~(a(1) & a(3))
|
||||
val a12 = ~(a(1) & ~a(2))
|
||||
|
||||
val r3 = ((a0123 & a4567)) // AND not NAND
|
||||
val r2 = (a0123)
|
||||
val r1 = (~(a01 | (~a23 & a45)))
|
||||
val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
|
||||
|
||||
val r = r3 ## r2 ## r1 ##r0
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_clz(in:Bits) : Bits = {
|
||||
val nlc7 = fun_clz_NLCi(in(31 downto 28))
|
||||
val nlc6 = fun_clz_NLCi(in(27 downto 24))
|
||||
val nlc5 = fun_clz_NLCi(in(23 downto 20))
|
||||
val nlc4 = fun_clz_NLCi(in(19 downto 16))
|
||||
val nlc3 = fun_clz_NLCi(in(15 downto 12))
|
||||
val nlc2 = fun_clz_NLCi(in(11 downto 8))
|
||||
val nlc1 = fun_clz_NLCi(in( 7 downto 4))
|
||||
val nlc0 = fun_clz_NLCi(in( 3 downto 0))
|
||||
val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
|
||||
val bne = fun_clz_BNE(a)
|
||||
|
||||
val muxo = (bne(2 downto 0)).mux(
|
||||
B"3'b000" -> nlc7(1 downto 0),
|
||||
B"3'b001" -> nlc6(1 downto 0),
|
||||
B"3'b010" -> nlc5(1 downto 0),
|
||||
B"3'b011" -> nlc4(1 downto 0),
|
||||
B"3'b100" -> nlc3(1 downto 0),
|
||||
B"3'b101" -> nlc2(1 downto 0),
|
||||
B"3'b110" -> nlc1(1 downto 0),
|
||||
B"3'b111" -> nlc0(1 downto 0)
|
||||
)
|
||||
val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
|
||||
|
||||
r.resize(32) // return value
|
||||
}
|
||||
// For trailing count, count using use leading count on bit-reversed value
|
||||
def fun_ctz(in:Bits) : Bits = {
|
||||
val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
|
||||
fun_clz(inr) // return value
|
||||
}
|
||||
|
||||
// naive popcnt
|
||||
def fun_popcnt(in:Bits) : Bits = {
|
||||
val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
|
||||
in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
|
||||
in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
|
||||
in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
|
||||
in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
|
||||
in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
|
||||
in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
|
||||
in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
//XPERMs
|
||||
def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(3 downto 0).asUInt
|
||||
val i1 = rs2(7 downto 4).asUInt
|
||||
val i2 = rs2(11 downto 8).asUInt
|
||||
val i3 = rs2(15 downto 12).asUInt
|
||||
val i4 = rs2(19 downto 16).asUInt
|
||||
val i5 = rs2(23 downto 20).asUInt
|
||||
val i6 = rs2(27 downto 24).asUInt
|
||||
val i7 = rs2(31 downto 28).asUInt
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r4 = (i4).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r5 = (i5).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r6 = (i6).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r7 = (i7).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(7 downto 0).asUInt;
|
||||
val i1 = rs2(15 downto 8).asUInt;
|
||||
val i2 = rs2(23 downto 16).asUInt;
|
||||
val i3 = rs2(31 downto 24).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(15 downto 0).asUInt;
|
||||
val i1 = rs2(31 downto 16).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
r1 ## r0 // return value
|
||||
}
|
||||
|
||||
def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbfPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbfPlugin._
|
||||
object IS_BitManipZbf extends Stageable(Bool)
|
||||
object BitManipZbf_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbf -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZbf -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbf -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbf -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbf -> True
|
||||
)
|
||||
def PACK_KEY = M"0000100----------100-----0110011"
|
||||
def PACKH_KEY = M"0000100----------111-----0110011"
|
||||
def BFP_KEY = M"0100100----------111-----0110011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZbf, False)
|
||||
decoderService.add(List(
|
||||
PACK_KEY -> (binaryActions ++ List(BitManipZbfCtrl -> BitManipZbfCtrlEnum.CTRL_pack, BitManipZbfCtrlpack -> BitManipZbfCtrlpackEnum.CTRL_PACK)),
|
||||
PACKH_KEY -> (binaryActions ++ List(BitManipZbfCtrl -> BitManipZbfCtrlEnum.CTRL_pack, BitManipZbfCtrlpack -> BitManipZbfCtrlpackEnum.CTRL_PACKH)),
|
||||
BFP_KEY -> (binaryActions ++ List(BitManipZbfCtrl -> BitManipZbfCtrlEnum.CTRL_BFP))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_pack = input(BitManipZbfCtrlpack).mux(
|
||||
BitManipZbfCtrlpackEnum.CTRL_PACK -> (input(SRC2)(15 downto 0) ## input(SRC1)(15 downto 0)).asBits,
|
||||
BitManipZbfCtrlpackEnum.CTRL_PACKH -> B"16'x0000" ## (input(SRC2)(7 downto 0) ## input(SRC1)(7 downto 0)).asBits
|
||||
) // mux pack
|
||||
insert(BitManipZbf_FINAL_OUTPUT) := input(BitManipZbfCtrl).mux(
|
||||
BitManipZbfCtrlEnum.CTRL_pack -> val_pack.asBits,
|
||||
BitManipZbfCtrlEnum.CTRL_BFP -> fun_bfp(input(SRC1), input(SRC2)).asBits
|
||||
) // primary mux
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZbf)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbf_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
428
BitManipZbs.scala
Normal file
428
BitManipZbs.scala
Normal file
|
|
@ -0,0 +1,428 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbsPlugin {
|
||||
object BitManipZbsCtrlsinglebitEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_BCLR, CTRL_BEXT, CTRL_BINV, CTRL_BSET = newElement()
|
||||
}
|
||||
object BitManipZbsCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_singlebit = newElement()
|
||||
}
|
||||
object BitManipZbsCtrlsinglebit extends Stageable(BitManipZbsCtrlsinglebitEnum())
|
||||
object BitManipZbsCtrl extends Stageable(BitManipZbsCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
def fun_grev( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized OR-combine
|
||||
def fun_gorc( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
|
||||
// helper function for the implementation of the generalized shuffles
|
||||
def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
|
||||
val x = src & ~(maskL | maskR)
|
||||
val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
|
||||
x2 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized shuffle
|
||||
def fun_shfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
|
||||
val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
|
||||
val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
|
||||
val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized unshuffle
|
||||
def fun_unshfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
|
||||
val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
|
||||
val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
|
||||
// this is trying to look like DOI 10.2478/jee-2015-0054
|
||||
def fun_clz_NLCi(x:Bits): Bits = {
|
||||
val r2 = (~(x(0) | x(1) | x(2) | x(3)))
|
||||
val r1 = (~(x(2) | x(3)))
|
||||
val r0 = (~(x(3) | (x(1) & ~x(2))))
|
||||
val r = r2 ## r1 ## r0
|
||||
r // return value
|
||||
}
|
||||
def fun_clz_BNE(a:Bits) : Bits = {
|
||||
val a01 = ~(a(0) & a(1))
|
||||
val a23 = ~(a(2) & a(3))
|
||||
|
||||
val a45 = ~(a(4) & a(5))
|
||||
val a67 = ~(a(6) & a(7))
|
||||
|
||||
val a0123 = ~(a01 | a23) // also r(2)
|
||||
val a4567 = ~(a45 | a67)
|
||||
|
||||
val a56 = ~(a(5) & ~a(6))
|
||||
val a024 = (a(0) & a(2) & a(4)) // AND not NAND
|
||||
val a13 = ~(a(1) & a(3))
|
||||
val a12 = ~(a(1) & ~a(2))
|
||||
|
||||
val r3 = ((a0123 & a4567)) // AND not NAND
|
||||
val r2 = (a0123)
|
||||
val r1 = (~(a01 | (~a23 & a45)))
|
||||
val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
|
||||
|
||||
val r = r3 ## r2 ## r1 ##r0
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_clz(in:Bits) : Bits = {
|
||||
val nlc7 = fun_clz_NLCi(in(31 downto 28))
|
||||
val nlc6 = fun_clz_NLCi(in(27 downto 24))
|
||||
val nlc5 = fun_clz_NLCi(in(23 downto 20))
|
||||
val nlc4 = fun_clz_NLCi(in(19 downto 16))
|
||||
val nlc3 = fun_clz_NLCi(in(15 downto 12))
|
||||
val nlc2 = fun_clz_NLCi(in(11 downto 8))
|
||||
val nlc1 = fun_clz_NLCi(in( 7 downto 4))
|
||||
val nlc0 = fun_clz_NLCi(in( 3 downto 0))
|
||||
val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
|
||||
val bne = fun_clz_BNE(a)
|
||||
|
||||
val muxo = (bne(2 downto 0)).mux(
|
||||
B"3'b000" -> nlc7(1 downto 0),
|
||||
B"3'b001" -> nlc6(1 downto 0),
|
||||
B"3'b010" -> nlc5(1 downto 0),
|
||||
B"3'b011" -> nlc4(1 downto 0),
|
||||
B"3'b100" -> nlc3(1 downto 0),
|
||||
B"3'b101" -> nlc2(1 downto 0),
|
||||
B"3'b110" -> nlc1(1 downto 0),
|
||||
B"3'b111" -> nlc0(1 downto 0)
|
||||
)
|
||||
val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
|
||||
|
||||
r.resize(32) // return value
|
||||
}
|
||||
// For trailing count, count using use leading count on bit-reversed value
|
||||
def fun_ctz(in:Bits) : Bits = {
|
||||
val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
|
||||
fun_clz(inr) // return value
|
||||
}
|
||||
|
||||
// naive popcnt
|
||||
def fun_popcnt(in:Bits) : Bits = {
|
||||
val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
|
||||
in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
|
||||
in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
|
||||
in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
|
||||
in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
|
||||
in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
|
||||
in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
|
||||
in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
//XPERMs
|
||||
def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(3 downto 0).asUInt
|
||||
val i1 = rs2(7 downto 4).asUInt
|
||||
val i2 = rs2(11 downto 8).asUInt
|
||||
val i3 = rs2(15 downto 12).asUInt
|
||||
val i4 = rs2(19 downto 16).asUInt
|
||||
val i5 = rs2(23 downto 20).asUInt
|
||||
val i6 = rs2(27 downto 24).asUInt
|
||||
val i7 = rs2(31 downto 28).asUInt
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r4 = (i4).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r5 = (i5).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r6 = (i6).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r7 = (i7).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(7 downto 0).asUInt;
|
||||
val i1 = rs2(15 downto 8).asUInt;
|
||||
val i2 = rs2(23 downto 16).asUInt;
|
||||
val i3 = rs2(31 downto 24).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(15 downto 0).asUInt;
|
||||
val i1 = rs2(31 downto 16).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
r1 ## r0 // return value
|
||||
}
|
||||
|
||||
def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbsPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbsPlugin._
|
||||
object IS_BitManipZbs extends Stageable(Bool)
|
||||
object BitManipZbs_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbs -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZbs -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbs -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbs -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbs -> True
|
||||
)
|
||||
def BCLR_KEY = M"0100100----------001-----0110011"
|
||||
def BSET_KEY = M"0010100----------001-----0110011"
|
||||
def BINV_KEY = M"0110100----------001-----0110011"
|
||||
def BEXT_KEY = M"0100100----------101-----0110011"
|
||||
def BCLRI_KEY = M"01001------------001-----0010011"
|
||||
def BSETI_KEY = M"00101------------001-----0010011"
|
||||
def BINVI_KEY = M"01101------------001-----0010011"
|
||||
def BEXTI_KEY = M"01001------------101-----0010011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZbs, False)
|
||||
decoderService.add(List(
|
||||
BCLR_KEY -> (binaryActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BCLR)),
|
||||
BSET_KEY -> (binaryActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BSET)),
|
||||
BINV_KEY -> (binaryActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BINV)),
|
||||
BEXT_KEY -> (binaryActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BEXT)),
|
||||
BCLRI_KEY -> (immediateActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BCLR)),
|
||||
BSETI_KEY -> (immediateActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BSET)),
|
||||
BINVI_KEY -> (immediateActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BINV)),
|
||||
BEXTI_KEY -> (immediateActions ++ List(BitManipZbsCtrl -> BitManipZbsCtrlEnum.CTRL_singlebit, BitManipZbsCtrlsinglebit -> BitManipZbsCtrlsinglebitEnum.CTRL_BEXT))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_singlebit = input(BitManipZbsCtrlsinglebit).mux(
|
||||
BitManipZbsCtrlsinglebitEnum.CTRL_BCLR -> (input(SRC1) & ~(B"32'x00000001"|<<((input(SRC2)&31).asUInt))).asBits,
|
||||
BitManipZbsCtrlsinglebitEnum.CTRL_BEXT -> ((input(SRC1) |>> ((input(SRC2)&31).asUInt)) & B"32'x00000001").asBits,
|
||||
BitManipZbsCtrlsinglebitEnum.CTRL_BINV -> (input(SRC1) ^ (B"32'x00000001"|<<((input(SRC2)&31).asUInt))).asBits,
|
||||
BitManipZbsCtrlsinglebitEnum.CTRL_BSET -> (input(SRC1) | (B"32'x00000001"|<<((input(SRC2)&31).asUInt))).asBits
|
||||
) // mux singlebit
|
||||
insert(BitManipZbs_FINAL_OUTPUT) := val_singlebit.asBits
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZbs)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbs_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
422
BitManipZbt.scala
Normal file
422
BitManipZbt.scala
Normal file
|
|
@ -0,0 +1,422 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object BitManipZbtPlugin {
|
||||
object BitManipZbtCtrlternaryEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_CMIX, CTRL_CMOV, CTRL_FSL, CTRL_FSR = newElement()
|
||||
}
|
||||
object BitManipZbtCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_ternary = newElement()
|
||||
}
|
||||
object BitManipZbtCtrlternary extends Stageable(BitManipZbtCtrlternaryEnum())
|
||||
object BitManipZbtCtrl extends Stageable(BitManipZbtCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
// function implementing the semantic of 32-bits generalized reverse
|
||||
def fun_grev( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized OR-combine
|
||||
def fun_gorc( a:Bits, b:Bits ) : Bits = {
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
|
||||
val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
|
||||
val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
|
||||
val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
|
||||
x16 // return value
|
||||
}
|
||||
|
||||
// helper function for the implementation of the generalized shuffles
|
||||
def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
|
||||
val x = src & ~(maskL | maskR)
|
||||
val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
|
||||
x2 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized shuffle
|
||||
def fun_shfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
|
||||
val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
|
||||
val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
|
||||
val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
// function implementing the semantic of 32-bits generalized unshuffle
|
||||
def fun_unshfl32(a:Bits, b:Bits) : Bits = {
|
||||
val x = a;
|
||||
val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
|
||||
val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
|
||||
val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
|
||||
val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
|
||||
// this is trying to look like DOI 10.2478/jee-2015-0054
|
||||
def fun_clz_NLCi(x:Bits): Bits = {
|
||||
val r2 = (~(x(0) | x(1) | x(2) | x(3)))
|
||||
val r1 = (~(x(2) | x(3)))
|
||||
val r0 = (~(x(3) | (x(1) & ~x(2))))
|
||||
val r = r2 ## r1 ## r0
|
||||
r // return value
|
||||
}
|
||||
def fun_clz_BNE(a:Bits) : Bits = {
|
||||
val a01 = ~(a(0) & a(1))
|
||||
val a23 = ~(a(2) & a(3))
|
||||
|
||||
val a45 = ~(a(4) & a(5))
|
||||
val a67 = ~(a(6) & a(7))
|
||||
|
||||
val a0123 = ~(a01 | a23) // also r(2)
|
||||
val a4567 = ~(a45 | a67)
|
||||
|
||||
val a56 = ~(a(5) & ~a(6))
|
||||
val a024 = (a(0) & a(2) & a(4)) // AND not NAND
|
||||
val a13 = ~(a(1) & a(3))
|
||||
val a12 = ~(a(1) & ~a(2))
|
||||
|
||||
val r3 = ((a0123 & a4567)) // AND not NAND
|
||||
val r2 = (a0123)
|
||||
val r1 = (~(a01 | (~a23 & a45)))
|
||||
val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
|
||||
|
||||
val r = r3 ## r2 ## r1 ##r0
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_clz(in:Bits) : Bits = {
|
||||
val nlc7 = fun_clz_NLCi(in(31 downto 28))
|
||||
val nlc6 = fun_clz_NLCi(in(27 downto 24))
|
||||
val nlc5 = fun_clz_NLCi(in(23 downto 20))
|
||||
val nlc4 = fun_clz_NLCi(in(19 downto 16))
|
||||
val nlc3 = fun_clz_NLCi(in(15 downto 12))
|
||||
val nlc2 = fun_clz_NLCi(in(11 downto 8))
|
||||
val nlc1 = fun_clz_NLCi(in( 7 downto 4))
|
||||
val nlc0 = fun_clz_NLCi(in( 3 downto 0))
|
||||
val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
|
||||
val bne = fun_clz_BNE(a)
|
||||
|
||||
val muxo = (bne(2 downto 0)).mux(
|
||||
B"3'b000" -> nlc7(1 downto 0),
|
||||
B"3'b001" -> nlc6(1 downto 0),
|
||||
B"3'b010" -> nlc5(1 downto 0),
|
||||
B"3'b011" -> nlc4(1 downto 0),
|
||||
B"3'b100" -> nlc3(1 downto 0),
|
||||
B"3'b101" -> nlc2(1 downto 0),
|
||||
B"3'b110" -> nlc1(1 downto 0),
|
||||
B"3'b111" -> nlc0(1 downto 0)
|
||||
)
|
||||
val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
|
||||
|
||||
r.resize(32) // return value
|
||||
}
|
||||
// For trailing count, count using use leading count on bit-reversed value
|
||||
def fun_ctz(in:Bits) : Bits = {
|
||||
val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
|
||||
fun_clz(inr) // return value
|
||||
}
|
||||
|
||||
// naive popcnt
|
||||
def fun_popcnt(in:Bits) : Bits = {
|
||||
val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
|
||||
in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
|
||||
in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
|
||||
in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
|
||||
in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
|
||||
in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
|
||||
in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
|
||||
in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
//XPERMs
|
||||
def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(3 downto 0).asUInt
|
||||
val i1 = rs2(7 downto 4).asUInt
|
||||
val i2 = rs2(11 downto 8).asUInt
|
||||
val i3 = rs2(15 downto 12).asUInt
|
||||
val i4 = rs2(19 downto 16).asUInt
|
||||
val i5 = rs2(23 downto 20).asUInt
|
||||
val i6 = rs2(27 downto 24).asUInt
|
||||
val i7 = rs2(31 downto 28).asUInt
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r4 = (i4).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r5 = (i5).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r6 = (i6).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
val r7 = (i7).mux(
|
||||
0 -> rs1(3 downto 0),
|
||||
1 -> rs1(7 downto 4),
|
||||
2 -> rs1(11 downto 8),
|
||||
3 -> rs1(15 downto 12),
|
||||
4 -> rs1(19 downto 16),
|
||||
5 -> rs1(23 downto 20),
|
||||
6 -> rs1(27 downto 24),
|
||||
7 -> rs1(31 downto 28),
|
||||
default -> B"4'b0000"
|
||||
)
|
||||
r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(7 downto 0).asUInt;
|
||||
val i1 = rs2(15 downto 8).asUInt;
|
||||
val i2 = rs2(23 downto 16).asUInt;
|
||||
val i3 = rs2(31 downto 24).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r2 = (i2).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
val r3 = (i3).mux(
|
||||
0 -> rs1(7 downto 0),
|
||||
1 -> rs1(15 downto 8),
|
||||
2 -> rs1(23 downto 16),
|
||||
3 -> rs1(31 downto 24),
|
||||
default -> B"8'b00000000"
|
||||
)
|
||||
r3 ## r2 ## r1 ## r0 // return value
|
||||
}
|
||||
def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val i0 = rs2(15 downto 0).asUInt;
|
||||
val i1 = rs2(31 downto 16).asUInt;
|
||||
val r0 = (i0).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
val r1 = (i1).mux(
|
||||
0 -> rs1(15 downto 0),
|
||||
1 -> rs1(31 downto 16),
|
||||
default -> B"16'x0000"
|
||||
)
|
||||
r1 ## r0 // return value
|
||||
}
|
||||
|
||||
def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
|
||||
val rawshamt = (rs2 & B"32'x0000003F").asUInt
|
||||
val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
|
||||
val A = (shamt === rawshamt) ? (rs1) | (rs3)
|
||||
val B = (shamt === rawshamt) ? (rs3) | (rs1)
|
||||
val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZbtPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZbtPlugin._
|
||||
object IS_BitManipZbt extends Stageable(Bool)
|
||||
object BitManipZbt_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbt -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZbt -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZbt -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbt -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZbt -> True
|
||||
)
|
||||
def CMIX_KEY = M"-----11----------001-----0110011"
|
||||
def CMOV_KEY = M"-----11----------101-----0110011"
|
||||
def FSL_KEY = M"-----10----------001-----0110011"
|
||||
def FSR_KEY = M"-----10----------101-----0110011"
|
||||
def FSRI_KEY = M"-----1-----------101-----0010011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZbt, False)
|
||||
decoderService.add(List(
|
||||
CMIX_KEY -> (ternaryActions ++ List(BitManipZbtCtrl -> BitManipZbtCtrlEnum.CTRL_ternary, BitManipZbtCtrlternary -> BitManipZbtCtrlternaryEnum.CTRL_CMIX)),
|
||||
CMOV_KEY -> (ternaryActions ++ List(BitManipZbtCtrl -> BitManipZbtCtrlEnum.CTRL_ternary, BitManipZbtCtrlternary -> BitManipZbtCtrlternaryEnum.CTRL_CMOV)),
|
||||
FSL_KEY -> (ternaryActions ++ List(BitManipZbtCtrl -> BitManipZbtCtrlEnum.CTRL_ternary, BitManipZbtCtrlternary -> BitManipZbtCtrlternaryEnum.CTRL_FSL)),
|
||||
FSR_KEY -> (ternaryActions ++ List(BitManipZbtCtrl -> BitManipZbtCtrlEnum.CTRL_ternary, BitManipZbtCtrlternary -> BitManipZbtCtrlternaryEnum.CTRL_FSR)),
|
||||
FSRI_KEY -> (immTernaryActions ++ List(BitManipZbtCtrl -> BitManipZbtCtrlEnum.CTRL_ternary, BitManipZbtCtrlternary -> BitManipZbtCtrlternaryEnum.CTRL_FSR))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_ternary = input(BitManipZbtCtrlternary).mux(
|
||||
BitManipZbtCtrlternaryEnum.CTRL_CMIX -> ((input(SRC1) & input(SRC2)) | (input(SRC3) & ~input(SRC2))).asBits,
|
||||
BitManipZbtCtrlternaryEnum.CTRL_CMOV -> ((input(SRC2).asUInt =/= 0) ? input(SRC1) | input(SRC3)).asBits,
|
||||
BitManipZbtCtrlternaryEnum.CTRL_FSL -> fun_fsl(input(SRC1), input(SRC3), input(SRC2)).asBits,
|
||||
BitManipZbtCtrlternaryEnum.CTRL_FSR -> fun_fsr(input(SRC1), input(SRC3), input(SRC2)).asBits
|
||||
) // mux ternary
|
||||
insert(BitManipZbt_FINAL_OUTPUT) := val_ternary.asBits
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZbt)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZbt_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
33
Makefile
33
Makefile
|
|
@ -41,18 +41,43 @@ veryclean:
|
|||
ultraclean:
|
||||
rm -f $(OBJXX) $(OBJ) gen_plugin *~ inst_lex.c inst_par.c *.d *.scala
|
||||
|
||||
BitManipZbpPlugin.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZbp -i data_bitmanip.txt -I Zbp >| $@
|
||||
|
||||
BitManipAllPlugin.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipAll -i data_bitmanip.txt -I '*' >| $@
|
||||
|
||||
CryptoZknePlugin.scala: gen_plugin data_aes.txt
|
||||
./gen_plugin -n CryptoZkne -i data_aes.txt -I '*' >| $@
|
||||
|
||||
BitManipZba.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZba -i data_bitmanip.txt -I Zba >| $@
|
||||
|
||||
BitManipZbb.scala: gen_plugin data_bitmanip.txt data_bitmanip_ZbbOnly.txt
|
||||
./gen_plugin -n BitManipZbb -i data_bitmanip.txt -i data_bitmanip_ZbbOnly.txt -I Zbb >| $@
|
||||
|
||||
BitManipZbc.scala: gen_plugin data_clmul.txt
|
||||
./gen_plugin -n BitManipZbc -i data_clmul.txt -I Zbc >| $@
|
||||
|
||||
## Zbe unimplemented, b(de)compress are missing and pack[h] are in Zbf anyway
|
||||
|
||||
BitManipZbf.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZbf -i data_bitmanip.txt -I Zbf >| $@
|
||||
|
||||
## Zbm unimplemented, RV64 only
|
||||
|
||||
## includes both Zbb & Zbp to avoid redudancies as there is overlap
|
||||
## and Zpb has full version instructions with partial implementation
|
||||
## in Zbb
|
||||
## Should not be included along Zbb
|
||||
BitManipZbbZbp.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZbbZbp -i data_bitmanip.txt -I Zbb -I Zbp >| $@
|
||||
|
||||
## Zbr unimplemented, crc32* are missing
|
||||
|
||||
BitManipZbs.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZbs -i data_bitmanip.txt -I Zbs >| $@
|
||||
|
||||
BitManipZbt.scala: gen_plugin data_bitmanip.txt
|
||||
./gen_plugin -n BitManipZbt -i data_bitmanip.txt -I Zbt >| $@
|
||||
|
||||
CryptoZknh.scala: gen_plugin data_sha.txt
|
||||
./gen_plugin -n CryptoZknh -i data_sha.txt -I '*' >| $@
|
||||
|
||||
|
|
@ -66,6 +91,6 @@ P64DataProcess.scala: gen_plugin data_Zp64.txt
|
|||
./gen_plugin -w -n P64DataProcess -i data_Zp64.txt -I '*' >| $@
|
||||
|
||||
|
||||
scala: BitManipZbpPlugin.scala BitManipAllPlugin.scala CryptoZknePlugin.scala BitManipZbc.scala CryptoZknh.scala
|
||||
scala: BitManipAllPlugin.scala CryptoZknePlugin.scala CryptoZknh.scala BitManipZba.scala BitManipZbb.scala BitManipZbc.scala BitManipZbf.scala BitManipZbbZbp.scala BitManipZbs.scala BitManipZbt.scala
|
||||
|
||||
include $(DEPXX)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# B plugin generator for VexRiscv
|
||||
|
||||
**beware** This is targeting the bitmanip extension (B) on an intermediate draft from January 20, 2021, so opcodes and subsets might be not match the current version of B. Ditto for Z, this is targeting version 0.8.1. Both may require feature patch to VexRiscv, see below.
|
||||
**beware** This is targeting the bitmanip extension (B) on an intermediate draft from January 20, 2021, so opcodes and subsets might be not match the current version of B. Ditto for Z, this is targeting version 0.8.1. Both may require feature patch to VexRiscv, see below. Packed SIMD (P) stuff is missing a lot of feature and targets 0.92.
|
||||
|
||||
## This repository
|
||||
|
||||
|
|
@ -14,13 +14,15 @@ The generated plugin is for RV32 only. It doesn't yet support all B instructions
|
|||
* CRC32*
|
||||
* Three-operands instructions (CMIX, CMOV, FS[RL]*); they are available but need a VexRiscv patch to support the third input
|
||||
|
||||
There is no support for 'partial' instruction - implementing only a subset of the functionality of one instruction. So `grev` is supported, but `rev8` alone isn't. Subextension are defined without 'partial' instructions - so Zbb doesn't have `rev8` or `orc.B`.
|
||||
There is support for partial instructions (rev8, zext.h, orc.b) so that the default plugins generated for Zba, Zbb and Zbc should be feature-complete.
|
||||
|
||||
This has received limited testing in a [Linux-on-Litex-VexRiscv](https://github.com/litex-hub/linux-on-litex-vexriscv) SoC. YMMV. SMP mode was tested as well.
|
||||
|
||||
Also, the implementations of the instructions in SpinalHDL are written for tuncitonality, and not tuned or optimized in any way for performance/area/... (file usage.txt has some numbers).
|
||||
|
||||
A separate data file includes prototype support for RV32Zkne (AES encryption instructions) and RV32Zknh (SHA hash instructions) from the K extension draft 0.8.1. This requires another patch to VexRiscv, as Zkne uses field rs1 instead of rd for the output register.
|
||||
A separate data file include prototype support for RV32Zkne (AES encryption instructions) and RV32Zknh (SHA hash instructions) from the [K ("crypto")](https://github.com/riscv/riscv-crypto) extension draft 0.8.1. This requires another patch to VexRiscv, as Zkne uses field rs1 instead of rd for the output register.
|
||||
|
||||
There's also some experimental support for some [P ("packed SIMD")](https://github.com/riscv/riscv-p-spec) instructions. It requires even more patches to VexRiscv, first to use a third input sourced from the destination register (so not R4 format like B's ternaries), and second to enable Zp64 instructions that write to two registers (x(2n) and x(2n+1)).
|
||||
|
||||
## How to use
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
// Avoids non-ASCII (7 bit) characters, as some string ends up in SpinalHDL code
|
||||
//
|
||||
// Known differences with the specifications:
|
||||
// Zbb: doesn't include pack (to implement zext.h), grevi (to implement rev8), gorci (to implement orc.b)
|
||||
// Zbb: doesn't include pack (to implement zext.h), grevi (to implement rev8), gorci (to implement orc.b) -> see data_bitmanip_ZbbOnly.txt
|
||||
// Zbp:
|
||||
// Zbs:
|
||||
// Zba:
|
||||
|
|
|
|||
37
data_bitmanip_ZbbOnly.txt
Normal file
37
data_bitmanip_ZbbOnly.txt
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
// This is the specialized version of some more general instructions
|
||||
// That are included by default in Zbb
|
||||
// Those should not be combined with a plugin implementing the matching
|
||||
// base instruction(s)
|
||||
|
||||
//I PACK PACK 0000100----------100-----0110011 pack
|
||||
//I GORCI GORC 00101------------101-----0010011 grevorc
|
||||
//I GREVI GREV 01101------------101-----0010011 grevorc
|
||||
// ZEXT.H -> PACK w/ RS2 == 0
|
||||
I ZEXTdotH ZEXTdotH 000010000000-----100-----0110011 signextend Zbb
|
||||
// ORC.B -> GORCI w/ imm = 7 (0000111)
|
||||
I ORCdotB ORCdotB 001010000111-----101-----0010011 grevorc Zbb
|
||||
// REV8 -> GREVI w/ imm == 24 (0011000)
|
||||
I REV8 REV8 011010011000-----101-----0010011 grevorc Zbb
|
||||
|
||||
// SEMANTIC
|
||||
S REV8 "fun_rev8(input(SRC1))"
|
||||
S ORCdotB "fun_orcb(input(SRC1))"
|
||||
S ZEXTdotH "(B"16'x0000" ## input(SRC1)(15 downto 0))"
|
||||
|
||||
// PROLOGUE
|
||||
P """
|
||||
def fun_rev8(a:Bits) : Bits = {
|
||||
val r = a(7 downto 0) ## a(15 downto 8) ## a(23 downto 16) ## a(31 downto 24)
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_orcb(a:Bits) : Bits = {
|
||||
val x1 = (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1))
|
||||
val x2 = (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2))
|
||||
val x4 = (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4))
|
||||
|
||||
x4 // return value
|
||||
}
|
||||
"""
|
||||
|
||||
|
||||
19
unparse.cpp
19
unparse.cpp
|
|
@ -255,7 +255,7 @@ void unparse(std::ostream& output,
|
|||
output << '\t' << '\t' << '\t' << "import memory._" << std::endl;
|
||||
where = "memory";
|
||||
}
|
||||
|
||||
// 2nd level MUXes
|
||||
for (const group* g : *groups) {
|
||||
if (g->opnames.size() > 1) {
|
||||
output << '\t' << '\t' << '\t' << "val val_" << g->name << " = input("<< ctrlString << g->name << ").mux(" << std::endl;
|
||||
|
|
@ -273,23 +273,32 @@ void unparse(std::ostream& output,
|
|||
}
|
||||
}
|
||||
// conditional last level mux
|
||||
output << '\t' << '\t' << '\t' << "insert(" << outputString << ") := input(" << ctrlString << ").mux(" << std::endl;
|
||||
bool need_group = groups->size() > 1;
|
||||
if (need_group)
|
||||
output << '\t' << '\t' << '\t' << "insert(" << outputString << ") := input(" << ctrlString << ").mux(" << std::endl;
|
||||
else
|
||||
output << '\t' << '\t' << '\t' << "insert(" << outputString << ") := ";
|
||||
for (auto it = groups->begin() ; it != groups->end() ; it++) {
|
||||
group* g = *it;
|
||||
if (g->opnames.size() > 1) {
|
||||
output << '\t' << '\t' << '\t' << '\t' << ctrlEnumString << "." << g->ctrlName() << " -> val_" << g->name << ".asBits";
|
||||
if (need_group)
|
||||
output << '\t' << '\t' << '\t' << '\t' << ctrlEnumString << "." << g->ctrlName() << " -> ";
|
||||
output << "val_" << g->name << ".asBits";
|
||||
} else {
|
||||
std::string opname = *g->opnames.begin();
|
||||
std::string regName = prefix + "_INTERMEDIATE_" + opname + "" + std::to_string(em_widths[opname]);
|
||||
std::string semantic = two_cycles ? mem_semantics[opname] + "(input(" + regName + ")).asBits" : semantics[opname] + ".asBits";
|
||||
output << '\t' << '\t' << '\t' << '\t' << ctrlEnumString << ".CTRL_" << opname << " -> " << semantic;
|
||||
if (need_group)
|
||||
output << '\t' << '\t' << '\t' << '\t' << ctrlEnumString << ".CTRL_" << opname << " -> ";
|
||||
output << semantic;
|
||||
}
|
||||
if (std::next(it, 1) == groups->end())
|
||||
output << std::endl;
|
||||
else
|
||||
output << "," << std::endl;
|
||||
}
|
||||
output << '\t' << '\t' << '\t' << ") // primary mux" << std::endl;
|
||||
if (need_group)
|
||||
output << '\t' << '\t' << '\t' << ") // primary mux" << std::endl;
|
||||
output << '\t' << '\t' << "} // " << where << " plug newArea" << std::endl;
|
||||
if (!two_cycles) {
|
||||
output << '\t' << '\t' << "val injectionStage = if(earlyInjection) execute else memory" << std::endl;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue