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https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
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Update usage, add SM3 as it's an easy one
This commit is contained in:
Romain Dolbeau
parent
dc82c1f0ee
commit
b2b9087932
3 changed files with 181 additions and 25 deletions
3
Makefile
3
Makefile
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@ -102,6 +102,9 @@ CryptoZknh.scala: gen_plugin data_sha.txt
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## Zks, Zkr not supported
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CryptoSM3.scala: gen_plugin data_sm3.txt
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./gen_plugin -n CryptoSM3 -i data_sm3.txt -I '*' >| $@
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PDataProcess.scala: gen_plugin data_Zpn.txt
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./gen_plugin -n PDataProcess -i data_Zpn.txt -I Zpn >| $@
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20
data_sm3.txt
Normal file
20
data_sm3.txt
Normal file
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@ -0,0 +1,20 @@
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I SM3P0 SM3P0 000100001000-----001-----0010011 sm3 Zks
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I SM3P1 SM3P1 000100001001-----001-----0010011 sm3 Zks
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S SM3P0 "fun_sm3p0(input(SRC1))"
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S SM3P1 "fun_sm3p1(input(SRC1))"
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P """
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def fun_sm3p0(rs1: Bits) : Bits = {
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val rs1l9 = rs1(22 downto 0) ## rs1(31 downto 23)
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val rs1l17 = rs1(14 downto 0) ## rs1(31 downto 15)
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val r = rs1 ^ rs1l9 ^ rs1l17
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r // return value
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}
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def fun_sm3p1(rs1: Bits) : Bits = {
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val rs1l15 = rs1(16 downto 0) ## rs1(31 downto 17)
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val rs1l23 = rs1( 8 downto 0) ## rs1(31 downto 9)
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val r = rs1 ^ rs1l15 ^ rs1l23
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r // return value
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}
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"""
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183
usage.txt
183
usage.txt
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@ -1,31 +1,164 @@
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Usage in Artix-7 35T for the whole LiteX SoC without B:
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+----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs | 5400 | 0 | 20800 | 25.96 |
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| LUT as Logic | 5230 | 0 | 20800 | 25.14 |
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| LUT as Memory | 170 | 0 | 9600 | 1.77 |
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| LUT as Distributed RAM | 168 | 0 | | |
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| LUT as Shift Register | 2 | 0 | | |
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| Slice Registers | 4660 | 0 | 41600 | 11.20 |
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| Register as Flip Flop | 4660 | 0 | 41600 | 11.20 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 78 | 0 | 16300 | 0.48 |
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| F8 Muxes | 13 | 0 | 8150 | 0.16 |
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+----------------------------+------+-------+-----------+-------+
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As of VecRiscv commit 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9,
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plugin commit 8ad11036be11a77c261328233168ad080286da33.
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Set to 80 MHz as timings are constrained when using a lof
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of extra instructions. Usage from "utilization_place.rpt".
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Just one core.
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Usage in Artix-7 35T for the whole LiteX SoC with everything:
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1) Usage in Artix-7 35T for the whole LiteX SoC with no patch (C is disabled by default in VexRiscV, so rv32ima).
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+----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs | 8040 | 0 | 20800 | 38.65 |
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| LUT as Logic | 7870 | 0 | 20800 | 37.84 |
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| LUT as Memory | 170 | 0 | 9600 | 1.77 |
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| LUT as Distributed RAM | 168 | 0 | | |
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| LUT as Shift Register | 2 | 0 | | |
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| Slice Registers | 4688 | 0 | 41600 | 11.27 |
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| Register as Flip Flop | 4688 | 0 | 41600 | 11.27 |
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| Slice LUTs | 8142 | 0 | 20800 | 39.14 |
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| LUT as Logic | 7410 | 0 | 20800 | 35.63 |
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| LUT as Memory | 732 | 0 | 9600 | 7.63 |
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| LUT as Distributed RAM | 712 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 6845 | 0 | 41600 | 16.45 |
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| Register as Flip Flop | 6845 | 0 | 41600 | 16.45 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 251 | 0 | 16300 | 1.54 |
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| F8 Muxes | 85 | 0 | 8150 | 1.04 |
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| F7 Muxes | 69 | 0 | 16300 | 0.42 |
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| F8 Muxes | 5 | 0 | 8150 | 0.06 |
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+----------------------------+------+-------+-----------+-------+
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 21 | 0 | 50 | 42.00 |
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| RAMB36/FIFO* | 20 | 0 | 50 | 40.00 |
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| RAMB36E1 only | 20 | | | |
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| RAMB18 | 2 | 0 | 100 | 2.00 |
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| RAMB18E1 only | 2 | | | |
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+-------------------+------+-------+-----------+-------+
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+----------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------+------+-------+-----------+-------+
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| DSPs | 4 | 0 | 90 | 4.44 |
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| DSP48E1 only | 4 | | | |
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+----------------+------+-------+-----------+-------+
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2) Usage in Artix-7 35T for the whole LiteX SoC with patches to support extensions, csr access for the cycle counter, new EvenOdd register file but no additional instructions:
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+----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs | 8301 | 0 | 20800 | 39.91 |
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| LUT as Logic | 7521 | 0 | 20800 | 36.16 |
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| LUT as Memory | 780 | 0 | 9600 | 8.13 |
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| LUT as Distributed RAM | 760 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 6946 | 0 | 41600 | 16.70 |
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| Register as Flip Flop | 6946 | 0 | 41600 | 16.70 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 76 | 0 | 16300 | 0.47 |
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| F8 Muxes | 10 | 0 | 8150 | 0.12 |
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+----------------------------+------+-------+-----------+-------+
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(memory, DSP unchanged).
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3) Usage in Artix-7 35T for the whole LiteX SoC with the patches above in 2), plus:
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"new CryptoZkndPlugin(earlyInjection = false),
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new CryptoZknePlugin(earlyInjection = false),
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new CryptoZknhPlugin,"
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i.e. the Zkn extension
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+----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs | 8959 | 0 | 20800 | 43.07 |
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| LUT as Logic | 8179 | 0 | 20800 | 39.32 |
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| LUT as Memory | 780 | 0 | 9600 | 8.13 |
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| LUT as Distributed RAM | 760 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 7017 | 0 | 41600 | 16.87 |
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| Register as Flip Flop | 7017 | 0 | 41600 | 16.87 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 191 | 0 | 16300 | 1.17 |
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| F8 Muxes | 53 | 0 | 8150 | 0.65 |
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+----------------------------+------+-------+-----------+-------+
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(memory, DSP unchanged).
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4) Idem 3) but adding "new BitManipZbcPlugin(earlyInjection = false)," as well
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+----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs | 9430 | 0 | 20800 | 45.34 |
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| LUT as Logic | 8650 | 0 | 20800 | 41.59 |
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| LUT as Memory | 780 | 0 | 9600 | 8.13 |
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| LUT as Distributed RAM | 760 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 7051 | 0 | 41600 | 16.95 |
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| Register as Flip Flop | 7051 | 0 | 41600 | 16.95 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 194 | 0 | 16300 | 1.19 |
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| F8 Muxes | 53 | 0 | 8150 | 0.65 |
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+----------------------------+------+-------+-----------+-------+
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(memory, DSP unchanged).
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5) Usage in Artix-7 35T for the whole LiteX SoC with the patches above in 2), plus:
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"new BitManipZbaPlugin,
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new BitManipZbbZbpPlugin,
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new BitManipZbcPlugin(earlyInjection = false),
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new BitManipBFPOnlyPlugin,
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new BitManipZbsPlugin,
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new BitManipZbtPlugin,
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"
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i.e. all the supported B instructions that are in a subextension (slo/sro not present), but no crypto.
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs | 10735 | 0 | 20800 | 51.61 |
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| LUT as Logic | 9907 | 0 | 20800 | 47.63 |
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| LUT as Memory | 828 | 0 | 9600 | 8.63 |
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| LUT as Distributed RAM | 808 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 7036 | 0 | 41600 | 16.91 |
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| Register as Flip Flop | 7036 | 0 | 41600 | 16.91 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 101 | 0 | 16300 | 0.62 |
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| F8 Muxes | 11 | 0 | 8150 | 0.13 |
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+----------------------------+-------+-------+-----------+-------+
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(memory, DSP unchanged).
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6) Usage in Artix-7 35T for the whole LiteX SoC with the patches above in 2), plus the plugins listed in 3) & 5), i.e nearly everything.
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs | 11368 | 0 | 20800 | 54.65 |
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| LUT as Logic | 10540 | 0 | 20800 | 50.67 |
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| LUT as Memory | 828 | 0 | 9600 | 8.63 |
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| LUT as Distributed RAM | 808 | 0 | | |
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| LUT as Shift Register | 20 | 0 | | |
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| Slice Registers | 7109 | 0 | 41600 | 17.09 |
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| Register as Flip Flop | 7109 | 0 | 41600 | 17.09 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 192 | 0 | 16300 | 1.18 |
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| F8 Muxes | 53 | 0 | 8150 | 0.65 |
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+----------------------------+-------+-------+-----------+-------+
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(memory, DSP unchanged).
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7) Adding C, CryptoSM3 and going dual-core:
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs | 19641 | 0 | 20800 | 94.43 |
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| LUT as Logic | 18466 | 0 | 20800 | 88.78 |
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| LUT as Memory | 1175 | 0 | 9600 | 12.24 |
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| LUT as Distributed RAM | 1172 | 0 | | |
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| LUT as Shift Register | 3 | 0 | | |
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| Slice Registers | 11663 | 0 | 41600 | 28.04 |
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| Register as Flip Flop | 11663 | 0 | 41600 | 28.04 |
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| Register as Latch | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 470 | 0 | 16300 | 2.88 |
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| F8 Muxes | 93 | 0 | 8150 | 1.14 |
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+----------------------------+-------+-------+-----------+-------+
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 32 | 0 | 50 | 64.00 |
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| RAMB36/FIFO* | 26 | 0 | 50 | 52.00 |
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| RAMB36E1 only | 26 | | | |
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| RAMB18 | 12 | 0 | 100 | 12.00 |
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| RAMB18E1 only | 12 | | | |
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+-------------------+------+-------+-----------+-------+
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+----------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------+------+-------+-----------+-------+
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| DSPs | 8 | 0 | 90 | 8.89 |
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| DSP48E1 only | 8 | | | |
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+----------------+------+-------+-----------+-------+
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