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https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
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cleanup
This commit is contained in:
Romain Dolbeau
parent
143dfa1204
commit
ed8397a4b6
4 changed files with 1101 additions and 2 deletions
490
CryptoZkb.scala
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490
CryptoZkb.scala
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// WARNING: this is auto-generated code!
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// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
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package vexriscv.plugin
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import spinal.core._
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import vexriscv.{Stageable, DecoderService, VexRiscv}
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object BitManipZkbPlugin {
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object BitManipZkbCtrlbitwiseEnum extends SpinalEnum(binarySequential) {
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val CTRL_ANDN, CTRL_ORN, CTRL_XNOR = newElement()
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}
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object BitManipZkbCtrlrotationEnum extends SpinalEnum(binarySequential) {
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val CTRL_ROL, CTRL_ROR = newElement()
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}
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object BitManipZkbCtrlpackEnum extends SpinalEnum(binarySequential) {
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val CTRL_PACK, CTRL_PACKH, CTRL_PACKU = newElement()
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}
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object BitManipZkbCtrlxpermEnum extends SpinalEnum(binarySequential) {
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val CTRL_XPERMdotB, CTRL_XPERMdotN = newElement()
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}
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object BitManipZkbCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
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val CTRL_GORC, CTRL_REV8 = newElement()
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}
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object BitManipZkbCtrlEnum extends SpinalEnum(binarySequential) {
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val CTRL_bitwise, CTRL_rotation, CTRL_pack, CTRL_xperm, CTRL_grevorc = newElement()
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}
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object BitManipZkbCtrlbitwise extends Stageable(BitManipZkbCtrlbitwiseEnum())
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object BitManipZkbCtrlrotation extends Stageable(BitManipZkbCtrlrotationEnum())
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object BitManipZkbCtrlpack extends Stageable(BitManipZkbCtrlpackEnum())
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object BitManipZkbCtrlxperm extends Stageable(BitManipZkbCtrlxpermEnum())
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object BitManipZkbCtrlgrevorc extends Stageable(BitManipZkbCtrlgrevorcEnum())
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object BitManipZkbCtrl extends Stageable(BitManipZkbCtrlEnum())
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// Prologue
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// function implementing the semantic of 32-bits generalized reverse
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def fun_grev( a:Bits, b:Bits ) : Bits = {
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
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val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
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val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
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val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
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x16 // return value
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}
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// function implementing the semantic of 32-bits generalized OR-combine
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def fun_gorc( a:Bits, b:Bits ) : Bits = {
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
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val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
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val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
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val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
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x16 // return value
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}
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// helper function for the implementation of the generalized shuffles
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def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
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val x = src & ~(maskL | maskR)
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val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
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x2 // return value
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}
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// function implementing the semantic of 32-bits generalized shuffle
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def fun_shfl32(a:Bits, b:Bits) : Bits = {
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val x = a;
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val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
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val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
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val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
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val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
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x4 // return value
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}
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// function implementing the semantic of 32-bits generalized unshuffle
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def fun_unshfl32(a:Bits, b:Bits) : Bits = {
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val x = a;
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
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val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
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val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
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x4 // return value
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}
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// this is trying to look like DOI 10.2478/jee-2015-0054
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def fun_clz_NLCi(x:Bits): Bits = {
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val r2 = (~(x(0) | x(1) | x(2) | x(3)))
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val r1 = (~(x(2) | x(3)))
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val r0 = (~(x(3) | (x(1) & ~x(2))))
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val r = r2 ## r1 ## r0
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r // return value
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}
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def fun_clz_BNE(a:Bits) : Bits = {
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val a01 = ~(a(0) & a(1))
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val a23 = ~(a(2) & a(3))
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val a45 = ~(a(4) & a(5))
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val a67 = ~(a(6) & a(7))
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val a0123 = ~(a01 | a23) // also r(2)
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val a4567 = ~(a45 | a67)
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val a56 = ~(a(5) & ~a(6))
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val a024 = (a(0) & a(2) & a(4)) // AND not NAND
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val a13 = ~(a(1) & a(3))
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val a12 = ~(a(1) & ~a(2))
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val r3 = ((a0123 & a4567)) // AND not NAND
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val r2 = (a0123)
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val r1 = (~(a01 | (~a23 & a45)))
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val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
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val r = r3 ## r2 ## r1 ##r0
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r // return value
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}
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def fun_clz(in:Bits) : Bits = {
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val nlc7 = fun_clz_NLCi(in(31 downto 28))
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val nlc6 = fun_clz_NLCi(in(27 downto 24))
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val nlc5 = fun_clz_NLCi(in(23 downto 20))
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val nlc4 = fun_clz_NLCi(in(19 downto 16))
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val nlc3 = fun_clz_NLCi(in(15 downto 12))
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val nlc2 = fun_clz_NLCi(in(11 downto 8))
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val nlc1 = fun_clz_NLCi(in( 7 downto 4))
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val nlc0 = fun_clz_NLCi(in( 3 downto 0))
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val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
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val bne = fun_clz_BNE(a)
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val muxo = (bne(2 downto 0)).mux(
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B"3'b000" -> nlc7(1 downto 0),
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B"3'b001" -> nlc6(1 downto 0),
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B"3'b010" -> nlc5(1 downto 0),
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B"3'b011" -> nlc4(1 downto 0),
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B"3'b100" -> nlc3(1 downto 0),
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B"3'b101" -> nlc2(1 downto 0),
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B"3'b110" -> nlc1(1 downto 0),
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B"3'b111" -> nlc0(1 downto 0)
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)
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val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
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r.resize(32) // return value
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}
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// For trailing count, count using use leading count on bit-reversed value
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def fun_ctz(in:Bits) : Bits = {
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val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
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fun_clz(inr) // return value
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}
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// naive popcnt
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def fun_popcnt(in:Bits) : Bits = {
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val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
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in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
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in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
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in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
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in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
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in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
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in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
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in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
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r.asBits.resize(32) // return value
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}
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//XPERMs
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def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(3 downto 0).asUInt
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val i1 = rs2(7 downto 4).asUInt
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val i2 = rs2(11 downto 8).asUInt
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val i3 = rs2(15 downto 12).asUInt
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val i4 = rs2(19 downto 16).asUInt
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val i5 = rs2(23 downto 20).asUInt
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val i6 = rs2(27 downto 24).asUInt
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val i7 = rs2(31 downto 28).asUInt
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val r0 = (i0).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r1 = (i1).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r2 = (i2).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r3 = (i3).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r4 = (i4).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r5 = (i5).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r6 = (i6).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r7 = (i7).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
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}
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def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(7 downto 0).asUInt;
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val i1 = rs2(15 downto 8).asUInt;
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val i2 = rs2(23 downto 16).asUInt;
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val i3 = rs2(31 downto 24).asUInt;
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val r0 = (i0).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r1 = (i1).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r2 = (i2).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r3 = (i3).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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r3 ## r2 ## r1 ## r0 // return value
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}
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def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(15 downto 0).asUInt;
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val i1 = rs2(31 downto 16).asUInt;
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val r0 = (i0).mux(
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0 -> rs1(15 downto 0),
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1 -> rs1(31 downto 16),
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default -> B"16'x0000"
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)
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val r1 = (i1).mux(
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0 -> rs1(15 downto 0),
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1 -> rs1(31 downto 16),
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default -> B"16'x0000"
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)
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r1 ## r0 // return value
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}
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def fun_fsl(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
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val rawshamt = (rs2 & B"32'x0000003F").asUInt
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val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
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val A = (shamt === rawshamt) ? (rs1) | (rs3)
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val B = (shamt === rawshamt) ? (rs3) | (rs1)
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val r = (shamt === 0) ? (A) | ((A |<< shamt) | (B |>> (32-shamt)))
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r // return value
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}
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def fun_fsr(rs1:Bits, rs3:Bits, rs2:Bits) : Bits = {
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val rawshamt = (rs2 & B"32'x0000003F").asUInt
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val shamt = (rawshamt >= 32) ? (rawshamt - 32) | (rawshamt)
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val A = (shamt === rawshamt) ? (rs1) | (rs3)
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val B = (shamt === rawshamt) ? (rs3) | (rs1)
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val r = (shamt === 0) ? (A) | ((A |>> shamt) | (B |<< (32-shamt)))
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||||
r // return value
|
||||
}
|
||||
|
||||
def fun_bfp(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val off = rs2(20 downto 16).asUInt
|
||||
val rawlen = rs2(27 downto 24).asUInt
|
||||
val convlen = (rawlen === 0) ? (rawlen+16) | (rawlen)
|
||||
val len = ((convlen + off) > 32) ? (32 - off) | (convlen)
|
||||
val allones = B"16'xFFFF"
|
||||
val lenones = (allones |>> (16-len))
|
||||
//val one = B"17'x00001"
|
||||
//val lenones = (((one |<< len).asUInt) - 1).asBits;
|
||||
val mask = (lenones.resize(32) |<< off);
|
||||
val data = (rs2 & lenones.resize(32)) |<< off;
|
||||
|
||||
val r = (rs1 & ~mask) | data
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
|
||||
def fun_rev8(a:Bits) : Bits = {
|
||||
val r = a(7 downto 0) ## a(15 downto 8) ## a(23 downto 16) ## a(31 downto 24)
|
||||
|
||||
r // return value
|
||||
}
|
||||
def fun_orcb(a:Bits) : Bits = {
|
||||
val x1 = (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1))
|
||||
val x2 = (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2))
|
||||
val x4 = (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4))
|
||||
|
||||
x4 // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class BitManipZkbPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import BitManipZkbPlugin._
|
||||
object IS_BitManipZkb extends Stageable(Bool)
|
||||
object BitManipZkb_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZkb -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_BitManipZkb -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_BitManipZkb -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZkb -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_BitManipZkb -> True
|
||||
)
|
||||
def ANDN_KEY = M"0100000----------111-----0110011"
|
||||
def ORN_KEY = M"0100000----------110-----0110011"
|
||||
def XNOR_KEY = M"0100000----------100-----0110011"
|
||||
def ROL_KEY = M"0110000----------001-----0110011"
|
||||
def ROR_KEY = M"0110000----------101-----0110011"
|
||||
def PACK_KEY = M"0000100----------100-----0110011"
|
||||
def PACKU_KEY = M"0100100----------100-----0110011"
|
||||
def PACKH_KEY = M"0000100----------111-----0110011"
|
||||
def XPERMdotN_KEY = M"0010100----------010-----0110011"
|
||||
def XPERMdotB_KEY = M"0010100----------100-----0110011"
|
||||
def RORI_KEY = M"01100------------101-----0010011"
|
||||
def GORCI_KEY = M"00101------------101-----0010011"
|
||||
def REV8_KEY = M"011010011000-----101-----0010011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_BitManipZkb, False)
|
||||
decoderService.add(List(
|
||||
ANDN_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_bitwise, BitManipZkbCtrlbitwise -> BitManipZkbCtrlbitwiseEnum.CTRL_ANDN)),
|
||||
ORN_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_bitwise, BitManipZkbCtrlbitwise -> BitManipZkbCtrlbitwiseEnum.CTRL_ORN)),
|
||||
XNOR_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_bitwise, BitManipZkbCtrlbitwise -> BitManipZkbCtrlbitwiseEnum.CTRL_XNOR)),
|
||||
ROL_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_rotation, BitManipZkbCtrlrotation -> BitManipZkbCtrlrotationEnum.CTRL_ROL)),
|
||||
ROR_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_rotation, BitManipZkbCtrlrotation -> BitManipZkbCtrlrotationEnum.CTRL_ROR)),
|
||||
RORI_KEY -> (immediateActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_rotation, BitManipZkbCtrlrotation -> BitManipZkbCtrlrotationEnum.CTRL_ROR)),
|
||||
PACK_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_pack, BitManipZkbCtrlpack -> BitManipZkbCtrlpackEnum.CTRL_PACK)),
|
||||
PACKU_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_pack, BitManipZkbCtrlpack -> BitManipZkbCtrlpackEnum.CTRL_PACKU)),
|
||||
PACKH_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_pack, BitManipZkbCtrlpack -> BitManipZkbCtrlpackEnum.CTRL_PACKH)),
|
||||
XPERMdotN_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_xperm, BitManipZkbCtrlxperm -> BitManipZkbCtrlxpermEnum.CTRL_XPERMdotN)),
|
||||
XPERMdotB_KEY -> (binaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_xperm, BitManipZkbCtrlxperm -> BitManipZkbCtrlxpermEnum.CTRL_XPERMdotB)),
|
||||
GORCI_KEY -> (immediateActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_grevorc, BitManipZkbCtrlgrevorc -> BitManipZkbCtrlgrevorcEnum.CTRL_GORC)),
|
||||
REV8_KEY -> (unaryActions ++ List(BitManipZkbCtrl -> BitManipZkbCtrlEnum.CTRL_grevorc, BitManipZkbCtrlgrevorc -> BitManipZkbCtrlgrevorcEnum.CTRL_REV8))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_bitwise = input(BitManipZkbCtrlbitwise).mux(
|
||||
BitManipZkbCtrlbitwiseEnum.CTRL_ANDN -> (input(SRC1) & ~input(SRC2)).asBits,
|
||||
BitManipZkbCtrlbitwiseEnum.CTRL_ORN -> (input(SRC1) | ~input(SRC2)).asBits,
|
||||
BitManipZkbCtrlbitwiseEnum.CTRL_XNOR -> (input(SRC1) ^ ~input(SRC2)).asBits
|
||||
) // mux bitwise
|
||||
val val_rotation = input(BitManipZkbCtrlrotation).mux(
|
||||
BitManipZkbCtrlrotationEnum.CTRL_ROL -> input(SRC1).rotateLeft((input(SRC2)&31)(4 downto 0).asUInt).asBits,
|
||||
BitManipZkbCtrlrotationEnum.CTRL_ROR -> input(SRC1).rotateRight((input(SRC2)&31)(4 downto 0).asUInt).asBits
|
||||
) // mux rotation
|
||||
val val_pack = input(BitManipZkbCtrlpack).mux(
|
||||
BitManipZkbCtrlpackEnum.CTRL_PACK -> (input(SRC2)(15 downto 0) ## input(SRC1)(15 downto 0)).asBits,
|
||||
BitManipZkbCtrlpackEnum.CTRL_PACKH -> B"16'x0000" ## (input(SRC2)(7 downto 0) ## input(SRC1)(7 downto 0)).asBits,
|
||||
BitManipZkbCtrlpackEnum.CTRL_PACKU -> (input(SRC2)(31 downto 16) ## input(SRC1)(31 downto 16)).asBits
|
||||
) // mux pack
|
||||
val val_xperm = input(BitManipZkbCtrlxperm).mux(
|
||||
BitManipZkbCtrlxpermEnum.CTRL_XPERMdotB -> fun_xperm_b(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZkbCtrlxpermEnum.CTRL_XPERMdotN -> fun_xperm_n(input(SRC1), input(SRC2)).asBits
|
||||
) // mux xperm
|
||||
val val_grevorc = input(BitManipZkbCtrlgrevorc).mux(
|
||||
BitManipZkbCtrlgrevorcEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)).asBits,
|
||||
BitManipZkbCtrlgrevorcEnum.CTRL_REV8 -> fun_rev8(input(SRC1)).asBits
|
||||
) // mux grevorc
|
||||
insert(BitManipZkb_FINAL_OUTPUT) := input(BitManipZkbCtrl).mux(
|
||||
BitManipZkbCtrlEnum.CTRL_bitwise -> val_bitwise.asBits,
|
||||
BitManipZkbCtrlEnum.CTRL_rotation -> val_rotation.asBits,
|
||||
BitManipZkbCtrlEnum.CTRL_pack -> val_pack.asBits,
|
||||
BitManipZkbCtrlEnum.CTRL_xperm -> val_xperm.asBits,
|
||||
BitManipZkbCtrlEnum.CTRL_grevorc -> val_grevorc.asBits
|
||||
) // primary mux
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_BitManipZkb)) {
|
||||
output(REGFILE_WRITE_DATA) := input(BitManipZkb_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
167
CryptoZkg.scala
Normal file
167
CryptoZkg.scala
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object CryptoZkgPlugin {
|
||||
object CryptoZkgCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_CLMUL = newElement()
|
||||
}
|
||||
object CryptoZkgCtrl extends Stageable(CryptoZkgCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
def fun_clmul(rs1:Bits, rs2:Bits) : Bits = {
|
||||
val x0 = (((rs2 & B"32'x00000001") =/= B"32'x00000000") ? (rs1 |<< 0) | (B"32'x00000000"))
|
||||
val x1 = (((rs2 & B"32'x00000002") =/= B"32'x00000000") ? (rs1 |<< 1) | (B"32'x00000000"))
|
||||
val x2 = (((rs2 & B"32'x00000004") =/= B"32'x00000000") ? (rs1 |<< 2) | (B"32'x00000000"))
|
||||
val x3 = (((rs2 & B"32'x00000008") =/= B"32'x00000000") ? (rs1 |<< 3) | (B"32'x00000000"))
|
||||
val x4 = (((rs2 & B"32'x00000010") =/= B"32'x00000000") ? (rs1 |<< 4) | (B"32'x00000000"))
|
||||
val x5 = (((rs2 & B"32'x00000020") =/= B"32'x00000000") ? (rs1 |<< 5) | (B"32'x00000000"))
|
||||
val x6 = (((rs2 & B"32'x00000040") =/= B"32'x00000000") ? (rs1 |<< 6) | (B"32'x00000000"))
|
||||
val x7 = (((rs2 & B"32'x00000080") =/= B"32'x00000000") ? (rs1 |<< 7) | (B"32'x00000000"))
|
||||
val x8 = (((rs2 & B"32'x00000100") =/= B"32'x00000000") ? (rs1 |<< 8) | (B"32'x00000000"))
|
||||
val x9 = (((rs2 & B"32'x00000200") =/= B"32'x00000000") ? (rs1 |<< 9) | (B"32'x00000000"))
|
||||
val x10 = (((rs2 & B"32'x00000400") =/= B"32'x00000000") ? (rs1 |<< 10) | (B"32'x00000000"))
|
||||
val x11 = (((rs2 & B"32'x00000800") =/= B"32'x00000000") ? (rs1 |<< 11) | (B"32'x00000000"))
|
||||
val x12 = (((rs2 & B"32'x00001000") =/= B"32'x00000000") ? (rs1 |<< 12) | (B"32'x00000000"))
|
||||
val x13 = (((rs2 & B"32'x00002000") =/= B"32'x00000000") ? (rs1 |<< 13) | (B"32'x00000000"))
|
||||
val x14 = (((rs2 & B"32'x00004000") =/= B"32'x00000000") ? (rs1 |<< 14) | (B"32'x00000000"))
|
||||
val x15 = (((rs2 & B"32'x00008000") =/= B"32'x00000000") ? (rs1 |<< 15) | (B"32'x00000000"))
|
||||
val x16 = (((rs2 & B"32'x00010000") =/= B"32'x00000000") ? (rs1 |<< 16) | (B"32'x00000000"))
|
||||
val x17 = (((rs2 & B"32'x00020000") =/= B"32'x00000000") ? (rs1 |<< 17) | (B"32'x00000000"))
|
||||
val x18 = (((rs2 & B"32'x00040000") =/= B"32'x00000000") ? (rs1 |<< 18) | (B"32'x00000000"))
|
||||
val x19 = (((rs2 & B"32'x00080000") =/= B"32'x00000000") ? (rs1 |<< 19) | (B"32'x00000000"))
|
||||
val x20 = (((rs2 & B"32'x00100000") =/= B"32'x00000000") ? (rs1 |<< 20) | (B"32'x00000000"))
|
||||
val x21 = (((rs2 & B"32'x00200000") =/= B"32'x00000000") ? (rs1 |<< 21) | (B"32'x00000000"))
|
||||
val x22 = (((rs2 & B"32'x00400000") =/= B"32'x00000000") ? (rs1 |<< 22) | (B"32'x00000000"))
|
||||
val x23 = (((rs2 & B"32'x00800000") =/= B"32'x00000000") ? (rs1 |<< 23) | (B"32'x00000000"))
|
||||
val x24 = (((rs2 & B"32'x01000000") =/= B"32'x00000000") ? (rs1 |<< 24) | (B"32'x00000000"))
|
||||
val x25 = (((rs2 & B"32'x02000000") =/= B"32'x00000000") ? (rs1 |<< 25) | (B"32'x00000000"))
|
||||
val x26 = (((rs2 & B"32'x04000000") =/= B"32'x00000000") ? (rs1 |<< 26) | (B"32'x00000000"))
|
||||
val x27 = (((rs2 & B"32'x08000000") =/= B"32'x00000000") ? (rs1 |<< 27) | (B"32'x00000000"))
|
||||
val x28 = (((rs2 & B"32'x10000000") =/= B"32'x00000000") ? (rs1 |<< 28) | (B"32'x00000000"))
|
||||
val x29 = (((rs2 & B"32'x20000000") =/= B"32'x00000000") ? (rs1 |<< 29) | (B"32'x00000000"))
|
||||
val x30 = (((rs2 & B"32'x40000000") =/= B"32'x00000000") ? (rs1 |<< 30) | (B"32'x00000000"))
|
||||
val x31 = (((rs2 & B"32'x80000000") =/= B"32'x00000000") ? (rs1 |<< 31) | (B"32'x00000000"))
|
||||
x0 ^ x1 ^ x2 ^ x3 ^ x4 ^ x5 ^ x6 ^ x7 ^ x8 ^ x9 ^ x10 ^ x11 ^ x12 ^ x13 ^ x14 ^ x15 ^ x16 ^ x17 ^ x18 ^ x19 ^ x20 ^ x21 ^ x22 ^ x23 ^ x24 ^ x25 ^ x26 ^ x27 ^ x28 ^ x29 ^ x30 ^ x31 // return value
|
||||
}
|
||||
|
||||
def fun_clmulrh(rs1:Bits, rs2:Bits, isH: Bool) : Bits = {
|
||||
val x0 = (((rs2 & B"32'x00000001") =/= B"32'x00000000") ? (rs1 |>> 31) | (B"32'x00000000"))
|
||||
val x1 = (((rs2 & B"32'x00000002") =/= B"32'x00000000") ? (rs1 |>> 30) | (B"32'x00000000"))
|
||||
val x2 = (((rs2 & B"32'x00000004") =/= B"32'x00000000") ? (rs1 |>> 29) | (B"32'x00000000"))
|
||||
val x3 = (((rs2 & B"32'x00000008") =/= B"32'x00000000") ? (rs1 |>> 28) | (B"32'x00000000"))
|
||||
val x4 = (((rs2 & B"32'x00000010") =/= B"32'x00000000") ? (rs1 |>> 27) | (B"32'x00000000"))
|
||||
val x5 = (((rs2 & B"32'x00000020") =/= B"32'x00000000") ? (rs1 |>> 26) | (B"32'x00000000"))
|
||||
val x6 = (((rs2 & B"32'x00000040") =/= B"32'x00000000") ? (rs1 |>> 25) | (B"32'x00000000"))
|
||||
val x7 = (((rs2 & B"32'x00000080") =/= B"32'x00000000") ? (rs1 |>> 24) | (B"32'x00000000"))
|
||||
val x8 = (((rs2 & B"32'x00000100") =/= B"32'x00000000") ? (rs1 |>> 23) | (B"32'x00000000"))
|
||||
val x9 = (((rs2 & B"32'x00000200") =/= B"32'x00000000") ? (rs1 |>> 22) | (B"32'x00000000"))
|
||||
val x10 = (((rs2 & B"32'x00000400") =/= B"32'x00000000") ? (rs1 |>> 21) | (B"32'x00000000"))
|
||||
val x11 = (((rs2 & B"32'x00000800") =/= B"32'x00000000") ? (rs1 |>> 20) | (B"32'x00000000"))
|
||||
val x12 = (((rs2 & B"32'x00001000") =/= B"32'x00000000") ? (rs1 |>> 19) | (B"32'x00000000"))
|
||||
val x13 = (((rs2 & B"32'x00002000") =/= B"32'x00000000") ? (rs1 |>> 18) | (B"32'x00000000"))
|
||||
val x14 = (((rs2 & B"32'x00004000") =/= B"32'x00000000") ? (rs1 |>> 17) | (B"32'x00000000"))
|
||||
val x15 = (((rs2 & B"32'x00008000") =/= B"32'x00000000") ? (rs1 |>> 16) | (B"32'x00000000"))
|
||||
val x16 = (((rs2 & B"32'x00010000") =/= B"32'x00000000") ? (rs1 |>> 15) | (B"32'x00000000"))
|
||||
val x17 = (((rs2 & B"32'x00020000") =/= B"32'x00000000") ? (rs1 |>> 14) | (B"32'x00000000"))
|
||||
val x18 = (((rs2 & B"32'x00040000") =/= B"32'x00000000") ? (rs1 |>> 13) | (B"32'x00000000"))
|
||||
val x19 = (((rs2 & B"32'x00080000") =/= B"32'x00000000") ? (rs1 |>> 12) | (B"32'x00000000"))
|
||||
val x20 = (((rs2 & B"32'x00100000") =/= B"32'x00000000") ? (rs1 |>> 11) | (B"32'x00000000"))
|
||||
val x21 = (((rs2 & B"32'x00200000") =/= B"32'x00000000") ? (rs1 |>> 10) | (B"32'x00000000"))
|
||||
val x22 = (((rs2 & B"32'x00400000") =/= B"32'x00000000") ? (rs1 |>> 9) | (B"32'x00000000"))
|
||||
val x23 = (((rs2 & B"32'x00800000") =/= B"32'x00000000") ? (rs1 |>> 8) | (B"32'x00000000"))
|
||||
val x24 = (((rs2 & B"32'x01000000") =/= B"32'x00000000") ? (rs1 |>> 7) | (B"32'x00000000"))
|
||||
val x25 = (((rs2 & B"32'x02000000") =/= B"32'x00000000") ? (rs1 |>> 6) | (B"32'x00000000"))
|
||||
val x26 = (((rs2 & B"32'x04000000") =/= B"32'x00000000") ? (rs1 |>> 5) | (B"32'x00000000"))
|
||||
val x27 = (((rs2 & B"32'x08000000") =/= B"32'x00000000") ? (rs1 |>> 4) | (B"32'x00000000"))
|
||||
val x28 = (((rs2 & B"32'x10000000") =/= B"32'x00000000") ? (rs1 |>> 3) | (B"32'x00000000"))
|
||||
val x29 = (((rs2 & B"32'x20000000") =/= B"32'x00000000") ? (rs1 |>> 2) | (B"32'x00000000"))
|
||||
val x30 = (((rs2 & B"32'x40000000") =/= B"32'x00000000") ? (rs1 |>> 1) | (B"32'x00000000"))
|
||||
val x31 = (((rs2 & B"32'x80000000") =/= B"32'x00000000") ? (rs1 |>> 0) | (B"32'x00000000"))
|
||||
val r = x0 ^ x1 ^ x2 ^ x3 ^ x4 ^ x5 ^ x6 ^ x7 ^ x8 ^ x9 ^ x10 ^ x11 ^ x12 ^ x13 ^ x14 ^ x15 ^ x16 ^ x17 ^ x18 ^ x19 ^ x20 ^ x21 ^ x22 ^ x23 ^ x24 ^ x25 ^ x26 ^ x27 ^ x28 ^ x29 ^ x30 ^ x31
|
||||
|
||||
isH ? (r |>> 1) | (r) // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class CryptoZkgPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import CryptoZkgPlugin._
|
||||
object IS_CryptoZkg extends Stageable(Bool)
|
||||
object CryptoZkg_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_CryptoZkg -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_CryptoZkg -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_CryptoZkg -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_CryptoZkg -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_CryptoZkg -> True
|
||||
)
|
||||
def CLMUL_KEY = M"0000101----------001-----0110011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_CryptoZkg, False)
|
||||
decoderService.add(List(
|
||||
CLMUL_KEY -> (binaryActions ++ List(CryptoZkgCtrl -> CryptoZkgCtrlEnum.CTRL_CLMUL))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
insert(CryptoZkg_FINAL_OUTPUT) := fun_clmul(input(SRC1),input(SRC2)).asBits
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_CryptoZkg)) {
|
||||
output(REGFILE_WRITE_DATA) := input(CryptoZkg_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
439
CryptoZks.scala
Normal file
439
CryptoZks.scala
Normal file
|
|
@ -0,0 +1,439 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object CryptoZksPlugin {
|
||||
object CryptoZksCtrlsm3Enum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SM3P0, CTRL_SM3P1 = newElement()
|
||||
}
|
||||
object CryptoZksCtrlsm4Enum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_SM4ED, CTRL_SM4KS = newElement()
|
||||
}
|
||||
object CryptoZksCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_sm3, CTRL_sm4 = newElement()
|
||||
}
|
||||
object CryptoZksCtrlsm3 extends Stageable(CryptoZksCtrlsm3Enum())
|
||||
object CryptoZksCtrlsm4 extends Stageable(CryptoZksCtrlsm4Enum())
|
||||
object CryptoZksCtrl extends Stageable(CryptoZksCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
def fun_sm3p0(rs1: Bits) : Bits = {
|
||||
val rs1l9 = rs1(22 downto 0) ## rs1(31 downto 23)
|
||||
val rs1l17 = rs1(14 downto 0) ## rs1(31 downto 15)
|
||||
val r = rs1 ^ rs1l9 ^ rs1l17
|
||||
r // return value
|
||||
}
|
||||
def fun_sm3p1(rs1: Bits) : Bits = {
|
||||
val rs1l15 = rs1(16 downto 0) ## rs1(31 downto 17)
|
||||
val rs1l23 = rs1( 8 downto 0) ## rs1(31 downto 9)
|
||||
val r = rs1 ^ rs1l15 ^ rs1l23
|
||||
r // return value
|
||||
}
|
||||
|
||||
|
||||
// massive MUX implementing SM4SBOX
|
||||
def fun_sm4sbox_raw(in:Bits) : Bits = {
|
||||
val x = in(7 downto 0)
|
||||
val r = (x).mux(
|
||||
B"8'x00" -> B"8'xD6",
|
||||
B"8'x01" -> B"8'x90",
|
||||
B"8'x02" -> B"8'xE9",
|
||||
B"8'x03" -> B"8'xFE",
|
||||
B"8'x04" -> B"8'xCC",
|
||||
B"8'x05" -> B"8'xE1",
|
||||
B"8'x06" -> B"8'x3D",
|
||||
B"8'x07" -> B"8'xB7",
|
||||
B"8'x08" -> B"8'x16",
|
||||
B"8'x09" -> B"8'xB6",
|
||||
B"8'x0a" -> B"8'x14",
|
||||
B"8'x0b" -> B"8'xC2",
|
||||
B"8'x0c" -> B"8'x28",
|
||||
B"8'x0d" -> B"8'xFB",
|
||||
B"8'x0e" -> B"8'x2C",
|
||||
B"8'x0f" -> B"8'x05",
|
||||
B"8'x10" -> B"8'x2B",
|
||||
B"8'x11" -> B"8'x67",
|
||||
B"8'x12" -> B"8'x9A",
|
||||
B"8'x13" -> B"8'x76",
|
||||
B"8'x14" -> B"8'x2A",
|
||||
B"8'x15" -> B"8'xBE",
|
||||
B"8'x16" -> B"8'x04",
|
||||
B"8'x17" -> B"8'xC3",
|
||||
B"8'x18" -> B"8'xAA",
|
||||
B"8'x19" -> B"8'x44",
|
||||
B"8'x1a" -> B"8'x13",
|
||||
B"8'x1b" -> B"8'x26",
|
||||
B"8'x1c" -> B"8'x49",
|
||||
B"8'x1d" -> B"8'x86",
|
||||
B"8'x1e" -> B"8'x06",
|
||||
B"8'x1f" -> B"8'x99",
|
||||
B"8'x20" -> B"8'x9C",
|
||||
B"8'x21" -> B"8'x42",
|
||||
B"8'x22" -> B"8'x50",
|
||||
B"8'x23" -> B"8'xF4",
|
||||
B"8'x24" -> B"8'x91",
|
||||
B"8'x25" -> B"8'xEF",
|
||||
B"8'x26" -> B"8'x98",
|
||||
B"8'x27" -> B"8'x7A",
|
||||
B"8'x28" -> B"8'x33",
|
||||
B"8'x29" -> B"8'x54",
|
||||
B"8'x2a" -> B"8'x0B",
|
||||
B"8'x2b" -> B"8'x43",
|
||||
B"8'x2c" -> B"8'xED",
|
||||
B"8'x2d" -> B"8'xCF",
|
||||
B"8'x2e" -> B"8'xAC",
|
||||
B"8'x2f" -> B"8'x62",
|
||||
B"8'x30" -> B"8'xE4",
|
||||
B"8'x31" -> B"8'xB3",
|
||||
B"8'x32" -> B"8'x1C",
|
||||
B"8'x33" -> B"8'xA9",
|
||||
B"8'x34" -> B"8'xC9",
|
||||
B"8'x35" -> B"8'x08",
|
||||
B"8'x36" -> B"8'xE8",
|
||||
B"8'x37" -> B"8'x95",
|
||||
B"8'x38" -> B"8'x80",
|
||||
B"8'x39" -> B"8'xDF",
|
||||
B"8'x3a" -> B"8'x94",
|
||||
B"8'x3b" -> B"8'xFA",
|
||||
B"8'x3c" -> B"8'x75",
|
||||
B"8'x3d" -> B"8'x8F",
|
||||
B"8'x3e" -> B"8'x3F",
|
||||
B"8'x3f" -> B"8'xA6",
|
||||
B"8'x40" -> B"8'x47",
|
||||
B"8'x41" -> B"8'x07",
|
||||
B"8'x42" -> B"8'xA7",
|
||||
B"8'x43" -> B"8'xFC",
|
||||
B"8'x44" -> B"8'xF3",
|
||||
B"8'x45" -> B"8'x73",
|
||||
B"8'x46" -> B"8'x17",
|
||||
B"8'x47" -> B"8'xBA",
|
||||
B"8'x48" -> B"8'x83",
|
||||
B"8'x49" -> B"8'x59",
|
||||
B"8'x4a" -> B"8'x3C",
|
||||
B"8'x4b" -> B"8'x19",
|
||||
B"8'x4c" -> B"8'xE6",
|
||||
B"8'x4d" -> B"8'x85",
|
||||
B"8'x4e" -> B"8'x4F",
|
||||
B"8'x4f" -> B"8'xA8",
|
||||
B"8'x50" -> B"8'x68",
|
||||
B"8'x51" -> B"8'x6B",
|
||||
B"8'x52" -> B"8'x81",
|
||||
B"8'x53" -> B"8'xB2",
|
||||
B"8'x54" -> B"8'x71",
|
||||
B"8'x55" -> B"8'x64",
|
||||
B"8'x56" -> B"8'xDA",
|
||||
B"8'x57" -> B"8'x8B",
|
||||
B"8'x58" -> B"8'xF8",
|
||||
B"8'x59" -> B"8'xEB",
|
||||
B"8'x5a" -> B"8'x0F",
|
||||
B"8'x5b" -> B"8'x4B",
|
||||
B"8'x5c" -> B"8'x70",
|
||||
B"8'x5d" -> B"8'x56",
|
||||
B"8'x5e" -> B"8'x9D",
|
||||
B"8'x5f" -> B"8'x35",
|
||||
B"8'x60" -> B"8'x1E",
|
||||
B"8'x61" -> B"8'x24",
|
||||
B"8'x62" -> B"8'x0E",
|
||||
B"8'x63" -> B"8'x5E",
|
||||
B"8'x64" -> B"8'x63",
|
||||
B"8'x65" -> B"8'x58",
|
||||
B"8'x66" -> B"8'xD1",
|
||||
B"8'x67" -> B"8'xA2",
|
||||
B"8'x68" -> B"8'x25",
|
||||
B"8'x69" -> B"8'x22",
|
||||
B"8'x6a" -> B"8'x7C",
|
||||
B"8'x6b" -> B"8'x3B",
|
||||
B"8'x6c" -> B"8'x01",
|
||||
B"8'x6d" -> B"8'x21",
|
||||
B"8'x6e" -> B"8'x78",
|
||||
B"8'x6f" -> B"8'x87",
|
||||
B"8'x70" -> B"8'xD4",
|
||||
B"8'x71" -> B"8'x00",
|
||||
B"8'x72" -> B"8'x46",
|
||||
B"8'x73" -> B"8'x57",
|
||||
B"8'x74" -> B"8'x9F",
|
||||
B"8'x75" -> B"8'xD3",
|
||||
B"8'x76" -> B"8'x27",
|
||||
B"8'x77" -> B"8'x52",
|
||||
B"8'x78" -> B"8'x4C",
|
||||
B"8'x79" -> B"8'x36",
|
||||
B"8'x7a" -> B"8'x02",
|
||||
B"8'x7b" -> B"8'xE7",
|
||||
B"8'x7c" -> B"8'xA0",
|
||||
B"8'x7d" -> B"8'xC4",
|
||||
B"8'x7e" -> B"8'xC8",
|
||||
B"8'x7f" -> B"8'x9E",
|
||||
B"8'x80" -> B"8'xEA",
|
||||
B"8'x81" -> B"8'xBF",
|
||||
B"8'x82" -> B"8'x8A",
|
||||
B"8'x83" -> B"8'xD2",
|
||||
B"8'x84" -> B"8'x40",
|
||||
B"8'x85" -> B"8'xC7",
|
||||
B"8'x86" -> B"8'x38",
|
||||
B"8'x87" -> B"8'xB5",
|
||||
B"8'x88" -> B"8'xA3",
|
||||
B"8'x89" -> B"8'xF7",
|
||||
B"8'x8a" -> B"8'xF2",
|
||||
B"8'x8b" -> B"8'xCE",
|
||||
B"8'x8c" -> B"8'xF9",
|
||||
B"8'x8d" -> B"8'x61",
|
||||
B"8'x8e" -> B"8'x15",
|
||||
B"8'x8f" -> B"8'xA1",
|
||||
B"8'x90" -> B"8'xE0",
|
||||
B"8'x91" -> B"8'xAE",
|
||||
B"8'x92" -> B"8'x5D",
|
||||
B"8'x93" -> B"8'xA4",
|
||||
B"8'x94" -> B"8'x9B",
|
||||
B"8'x95" -> B"8'x34",
|
||||
B"8'x96" -> B"8'x1A",
|
||||
B"8'x97" -> B"8'x55",
|
||||
B"8'x98" -> B"8'xAD",
|
||||
B"8'x99" -> B"8'x93",
|
||||
B"8'x9a" -> B"8'x32",
|
||||
B"8'x9b" -> B"8'x30",
|
||||
B"8'x9c" -> B"8'xF5",
|
||||
B"8'x9d" -> B"8'x8C",
|
||||
B"8'x9e" -> B"8'xB1",
|
||||
B"8'x9f" -> B"8'xE3",
|
||||
B"8'xa0" -> B"8'x1D",
|
||||
B"8'xa1" -> B"8'xF6",
|
||||
B"8'xa2" -> B"8'xE2",
|
||||
B"8'xa3" -> B"8'x2E",
|
||||
B"8'xa4" -> B"8'x82",
|
||||
B"8'xa5" -> B"8'x66",
|
||||
B"8'xa6" -> B"8'xCA",
|
||||
B"8'xa7" -> B"8'x60",
|
||||
B"8'xa8" -> B"8'xC0",
|
||||
B"8'xa9" -> B"8'x29",
|
||||
B"8'xaa" -> B"8'x23",
|
||||
B"8'xab" -> B"8'xAB",
|
||||
B"8'xac" -> B"8'x0D",
|
||||
B"8'xad" -> B"8'x53",
|
||||
B"8'xae" -> B"8'x4E",
|
||||
B"8'xaf" -> B"8'x6F",
|
||||
B"8'xb0" -> B"8'xD5",
|
||||
B"8'xb1" -> B"8'xDB",
|
||||
B"8'xb2" -> B"8'x37",
|
||||
B"8'xb3" -> B"8'x45",
|
||||
B"8'xb4" -> B"8'xDE",
|
||||
B"8'xb5" -> B"8'xFD",
|
||||
B"8'xb6" -> B"8'x8E",
|
||||
B"8'xb7" -> B"8'x2F",
|
||||
B"8'xb8" -> B"8'x03",
|
||||
B"8'xb9" -> B"8'xFF",
|
||||
B"8'xba" -> B"8'x6A",
|
||||
B"8'xbb" -> B"8'x72",
|
||||
B"8'xbc" -> B"8'x6D",
|
||||
B"8'xbd" -> B"8'x6C",
|
||||
B"8'xbe" -> B"8'x5B",
|
||||
B"8'xbf" -> B"8'x51",
|
||||
B"8'xc0" -> B"8'x8D",
|
||||
B"8'xc1" -> B"8'x1B",
|
||||
B"8'xc2" -> B"8'xAF",
|
||||
B"8'xc3" -> B"8'x92",
|
||||
B"8'xc4" -> B"8'xBB",
|
||||
B"8'xc5" -> B"8'xDD",
|
||||
B"8'xc6" -> B"8'xBC",
|
||||
B"8'xc7" -> B"8'x7F",
|
||||
B"8'xc8" -> B"8'x11",
|
||||
B"8'xc9" -> B"8'xD9",
|
||||
B"8'xca" -> B"8'x5C",
|
||||
B"8'xcb" -> B"8'x41",
|
||||
B"8'xcc" -> B"8'x1F",
|
||||
B"8'xcd" -> B"8'x10",
|
||||
B"8'xce" -> B"8'x5A",
|
||||
B"8'xcf" -> B"8'xD8",
|
||||
B"8'xd0" -> B"8'x0A",
|
||||
B"8'xd1" -> B"8'xC1",
|
||||
B"8'xd2" -> B"8'x31",
|
||||
B"8'xd3" -> B"8'x88",
|
||||
B"8'xd4" -> B"8'xA5",
|
||||
B"8'xd5" -> B"8'xCD",
|
||||
B"8'xd6" -> B"8'x7B",
|
||||
B"8'xd7" -> B"8'xBD",
|
||||
B"8'xd8" -> B"8'x2D",
|
||||
B"8'xd9" -> B"8'x74",
|
||||
B"8'xda" -> B"8'xD0",
|
||||
B"8'xdb" -> B"8'x12",
|
||||
B"8'xdc" -> B"8'xB8",
|
||||
B"8'xdd" -> B"8'xE5",
|
||||
B"8'xde" -> B"8'xB4",
|
||||
B"8'xdf" -> B"8'xB0",
|
||||
B"8'xe0" -> B"8'x89",
|
||||
B"8'xe1" -> B"8'x69",
|
||||
B"8'xe2" -> B"8'x97",
|
||||
B"8'xe3" -> B"8'x4A",
|
||||
B"8'xe4" -> B"8'x0C",
|
||||
B"8'xe5" -> B"8'x96",
|
||||
B"8'xe6" -> B"8'x77",
|
||||
B"8'xe7" -> B"8'x7E",
|
||||
B"8'xe8" -> B"8'x65",
|
||||
B"8'xe9" -> B"8'xB9",
|
||||
B"8'xea" -> B"8'xF1",
|
||||
B"8'xeb" -> B"8'x09",
|
||||
B"8'xec" -> B"8'xC5",
|
||||
B"8'xed" -> B"8'x6E",
|
||||
B"8'xee" -> B"8'xC6",
|
||||
B"8'xef" -> B"8'x84",
|
||||
B"8'xf0" -> B"8'x18",
|
||||
B"8'xf1" -> B"8'xF0",
|
||||
B"8'xf2" -> B"8'x7D",
|
||||
B"8'xf3" -> B"8'xEC",
|
||||
B"8'xf4" -> B"8'x3A",
|
||||
B"8'xf5" -> B"8'xDC",
|
||||
B"8'xf6" -> B"8'x4D",
|
||||
B"8'xf7" -> B"8'x20",
|
||||
B"8'xf8" -> B"8'x79",
|
||||
B"8'xf9" -> B"8'xEE",
|
||||
B"8'xfa" -> B"8'x5F",
|
||||
B"8'xfb" -> B"8'x3E",
|
||||
B"8'xfc" -> B"8'xD7",
|
||||
B"8'xfd" -> B"8'xCB",
|
||||
B"8'xfe" -> B"8'x39",
|
||||
B"8'xff" -> B"8'x48"
|
||||
)
|
||||
r // return value
|
||||
}
|
||||
def fun_sm4ed(rs1:Bits, rs2:Bits, sel: Bits) : Bits = {
|
||||
val idx = (sel).mux(
|
||||
B"2'b00" -> rs2( 7 downto 0),
|
||||
B"2'b01" -> rs2(15 downto 8),
|
||||
B"2'b10" -> rs2(23 downto 16),
|
||||
B"2'b11" -> rs2(31 downto 24)
|
||||
)
|
||||
val x = fun_sm4sbox_raw(idx)
|
||||
val y = x.resize(32) ^
|
||||
(x << 8).resize(32) ^
|
||||
(x << 2).resize(32) ^
|
||||
(x << 18).resize(32) ^
|
||||
((x & B"8'x3F") << 26).resize(32) ^
|
||||
((x & B"8'xC0") << 10).resize(32)
|
||||
val r = (sel).mux(
|
||||
B"2'b00" -> y(31 downto 0),
|
||||
B"2'b01" -> y(23 downto 0) ## y(31 downto 24),
|
||||
B"2'b10" -> y(15 downto 0) ## y(31 downto 16),
|
||||
B"2'b11" -> y( 7 downto 0) ## y(31 downto 8)
|
||||
)
|
||||
rs1 ^ r // return value
|
||||
}
|
||||
def fun_sm4ks(rs1:Bits, rs2:Bits, sel: Bits) : Bits = {
|
||||
val idx = (sel).mux(
|
||||
B"2'b00" -> rs2( 7 downto 0),
|
||||
B"2'b01" -> rs2(15 downto 8),
|
||||
B"2'b10" -> rs2(23 downto 16),
|
||||
B"2'b11" -> rs2(31 downto 24)
|
||||
)
|
||||
val x = fun_sm4sbox_raw(idx)
|
||||
val y = x.resize(32) ^
|
||||
((x & B"8'x07" ) << 29).resize(32) ^
|
||||
((x & B"8'xFE" ) << 7).resize(32) ^
|
||||
((x & B"8'x01" ) << 23).resize(32) ^
|
||||
((x & B"8'xF8" ) << 13).resize(32)
|
||||
val r = (sel).mux(
|
||||
B"2'b00" -> y(31 downto 0),
|
||||
B"2'b01" -> y(23 downto 0) ## y(31 downto 24),
|
||||
B"2'b10" -> y(15 downto 0) ## y(31 downto 16),
|
||||
B"2'b11" -> y( 7 downto 0) ## y(31 downto 8)
|
||||
)
|
||||
rs1 ^ r // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class CryptoZksPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import CryptoZksPlugin._
|
||||
object IS_CryptoZks extends Stageable(Bool)
|
||||
object CryptoZks_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_CryptoZks -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_CryptoZks -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_CryptoZks -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_CryptoZks -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_CryptoZks -> True
|
||||
)
|
||||
def SM3P0_KEY = M"000100001000-----001-----0010011"
|
||||
def SM3P1_KEY = M"000100001001-----001-----0010011"
|
||||
def SM4ED_KEY = M"--11000----------000000000110011"
|
||||
def SM4KS_KEY = M"--11010----------000000000110011"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_CryptoZks, False)
|
||||
decoderService.add(List(
|
||||
SM3P0_KEY -> (unaryActions ++ List(CryptoZksCtrl -> CryptoZksCtrlEnum.CTRL_sm3, CryptoZksCtrlsm3 -> CryptoZksCtrlsm3Enum.CTRL_SM3P0)),
|
||||
SM3P1_KEY -> (unaryActions ++ List(CryptoZksCtrl -> CryptoZksCtrlEnum.CTRL_sm3, CryptoZksCtrlsm3 -> CryptoZksCtrlsm3Enum.CTRL_SM3P1)),
|
||||
SM4ED_KEY -> (binaryActions ++ List(CryptoZksCtrl -> CryptoZksCtrlEnum.CTRL_sm4, CryptoZksCtrlsm4 -> CryptoZksCtrlsm4Enum.CTRL_SM4ED)),
|
||||
SM4KS_KEY -> (binaryActions ++ List(CryptoZksCtrl -> CryptoZksCtrlEnum.CTRL_sm4, CryptoZksCtrlsm4 -> CryptoZksCtrlsm4Enum.CTRL_SM4KS))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_sm3 = input(CryptoZksCtrlsm3).mux(
|
||||
CryptoZksCtrlsm3Enum.CTRL_SM3P0 -> fun_sm3p0(input(SRC1)).asBits,
|
||||
CryptoZksCtrlsm3Enum.CTRL_SM3P1 -> fun_sm3p1(input(SRC1)).asBits
|
||||
) // mux sm3
|
||||
val val_sm4 = input(CryptoZksCtrlsm4).mux(
|
||||
CryptoZksCtrlsm4Enum.CTRL_SM4ED -> fun_sm4ed(input(SRC1), input(SRC2), input(INSTRUCTION)(31 downto 30)).asBits,
|
||||
CryptoZksCtrlsm4Enum.CTRL_SM4KS -> fun_sm4ks(input(SRC1), input(SRC2), input(INSTRUCTION)(31 downto 30)).asBits
|
||||
) // mux sm4
|
||||
insert(CryptoZks_FINAL_OUTPUT) := input(CryptoZksCtrl).mux(
|
||||
CryptoZksCtrlEnum.CTRL_sm3 -> val_sm3.asBits,
|
||||
CryptoZksCtrlEnum.CTRL_sm4 -> val_sm4.asBits
|
||||
) // primary mux
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_CryptoZks)) {
|
||||
output(REGFILE_WRITE_DATA) := input(CryptoZks_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
7
Makefile
7
Makefile
|
|
@ -100,7 +100,10 @@ CryptoZkne.scala: gen_plugin data_aes.txt
|
|||
CryptoZknh.scala: gen_plugin data_sha.txt
|
||||
./gen_plugin -n CryptoZknh -i data_sha.txt -I '*' >| $@
|
||||
|
||||
## Zks, Zkr not supported
|
||||
## Zkr not supported
|
||||
|
||||
CryptoZks.scala: gen_plugin data_sm3.txt data_sm4.txt
|
||||
./gen_plugin -n CryptoZks -i data_sm3.txt -i data_sm4.txt -I '*' >| $@
|
||||
|
||||
CryptoSM3.scala: gen_plugin data_sm3.txt
|
||||
./gen_plugin -n CryptoSM3 -i data_sm3.txt -I '*' >| $@
|
||||
|
|
@ -121,7 +124,7 @@ B: BitManipZba.scala BitManipZbb.scala BitManipZbc.scala BitManipZbf.scala BitMa
|
|||
|
||||
P: PDataProcess.scala PSlowDataProcess.scala P64DataProcess.scala
|
||||
|
||||
Z: CryptoZkg.scala CryptoZknd.scala CryptoZkne.scala CryptoZknh.scala
|
||||
Z: CryptoZkg.scala CryptoZknd.scala CryptoZkne.scala CryptoZknh.scala CryptoZks.scala
|
||||
|
||||
scala: B P Z
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue