mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
40 lines
884 B
Makefile
40 lines
884 B
Makefile
SRCs=riscv32.c try-anything.c
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OBJs=$(SRCs:.c=.o)
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SCLIBS=cpucycles.o kernelrandombytes.o
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include ../r5.mk
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R5IMA_OPT+=-I..
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R5B_OPT+=-I.. -DRV32B -DRV32K
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all: aes256ctr aes256ctr_small
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clean:
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rm -f $(OBJs) *.S try.o try_small.o riscv32.o aes256ctr aes256ctr_small
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%.o: %.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@
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try.o: try.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@
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try_small.o: try.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@ -DSMALL
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riscv32.S: riscv32.c
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$(R5B_GCC) $(R5B_OPT) $< -S -o $@
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riscv32.o: riscv32.S
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$(R5B_GCC) $(R5B_OPT) $< -c -o $@
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aes256ctr: $(OBJs) riscv32.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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aes256ctr_small: $(OBJs) riscv32.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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kernelrandombytes.o: random.cpp
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$(R5IMA_GXX) $(R5IMA_OPT) $< -c -o $@
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cpucycles.o: riscv.c
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$(R5IMA_GCC) $< -march=$(R5ISA) -mabi=$(R5ABI) -I. -O1 -c -o $@
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